Questions tagged [system-verilog]

SystemVerilog is a unified hardware design, specification, and verification language based on extensions to Verilog.

SystemVerilog is a unified hardware description language (hdl) and verification language. Its two primary uses are to describe logical circuits targeted towards field-programmable gate arrays (FPGAs - fpga), programmable logic devices (PLD) and application-specific integrated circuits (ASICs - asic) and to develop tests and environments to validate these circuit descriptions.

It is defined by IEEE 1800-2017 and with the exception of keywords, is a backwards-compatible superset of verilog, IEEE 1364-2005.

3298 questions

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How to connect SystemC model with SystemVerilog?

Say we have a SystemC model of decade counter and I want to verify SystemVerilog Counter RTL using SystemC model. How can we connect these two in SV/UVM based testbench so as to communicate between them.

system-verilog uvm systemc

asked Nov 02 '15 at 08:37

MayurKubavat

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2 answers

Bitwise-or all fields in Verilog struct

Let's say that I have an array of buses, each one carrying a struct like so: typedef struct packed { logic [31:0] piano_concerto_in_d_minor; logic [31:0] piano_concerto_in_c_minor; logic [7:0] nationality; }…

struct bit-manipulation verilog system-verilog

asked Oct 28 '15 at 20:20

John M

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Assign and Truncate Packed Arrays

Recently I've been coding an FFT module, and as you may think it requires a lot of wires. In order to simplify the code I'm trying to use packed arrays. But I got a problem in truncating and assigning. Suppose I have a 48-bit vector A, divided into…

arrays truncate system-verilog

asked Oct 26 '15 at 19:56

João

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1 answer

Randomly Map Bits in Verilog

I am trying to create a simple, synthesizable module that randomly maps bits of an output to bits of the input without duplicates. For example, something like this for 8-bit in/out: module Scrambler(in, out); parameter WIDTH = 8; input…

verilog fpga system-verilog

asked Oct 17 '15 at 22:52

Jim Fialho

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1 answer

Concurrent Assertion - UVM test dependency

I want to write concurrent assertion which starts after some register write is performed on the DUT from UVM testbench. class test extends uvm_test; bit flag; task run_phase(uvm_phase phase); //call register write task , data is chosen in a random…

system-verilog assertions uvm system-verilog-assertions

asked Oct 17 '15 at 05:09

sharvil111

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Precedence of chained unary operators in SVA assertions

For a tool, I'm trying to correctly parse SystemVerilog assertions, and am confused about the correct precedence for certain expressions. The SystemVerilog standard has a nice table where they say that not > until > always for precedence. But I…

system-verilog system-verilog-assertions

asked Oct 16 '15 at 18:00

Jared Davis

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1 answer

Using a file name string as a SystemVerilog interface parameter?

Is it possible to use a string as a SystemVerilog interface paramter. I have 4 instances of the same interface, and I was wondering if I can `include different assertion files for each instance. My interface looks like this: interface dai_if…

system-verilog

asked Oct 15 '15 at 09:56

Robert Owen

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1 answer

UVM configuration database error when binding interface assertions

I have 4 instances of a DAI interface in my testbench. I have been running some simulations with my created environment and have had no issues with errors. However, when I attempt to bind my assertions to the interface instances, I get an error…

system-verilog uvm

asked Oct 13 '15 at 08:31

Robert Owen

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2 answers

Verilog module outputs z's

I'm trying to make a parameter and module to AND two numbers together and return a result. However, I seem to be having troubles. My code is as follows: module main; reg signed [3:0] x; reg signed [3:0] y; wire [3:0] out1; ander…

bit-manipulation verilog system-verilog

asked Oct 08 '15 at 00:13

Vincent Chan

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3 answers

system verilog : Overridden members system verilog classes

class my_a; int member1 = 1; endclass class my_ea extends my_a; int member1 = 2; endclass Now when I do my_a A; my_ea EA; EA =new(); A=EA; EA = new(); has given handle to object of type my_ea to class variable EA. A=EA; passes the same handle…

class oop verilog system-verilog

asked Oct 06 '15 at 09:20

jinam shah

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1 answer

Wait for A Bit Change in Same Timestep in SV

Here is the code module m; bit x; initial begin fork begin wait(x == 1); wait(x == 0); end begin @(x == 1); @(x == 0); end #10 $display("Timeout"); join_any disable…

verilog system-verilog

asked Oct 01 '15 at 05:53

Karan Shah

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Unbounded (infinite) repetitions in transitions for covergroup bins

How can I define coverage bin for transition that might have many repetitions in it? What I'm trying to do is something like this: bins st = (2=> 3[* 1:$] => 2); Of course, this doesn't work. Simulators give error messages when compiling this line.…

system-verilog

asked Sep 29 '15 at 22:56

Convergent

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1 answer

Is it possible to access a derived class's method from a base class by using $cast in systemverilog?

I'm trying to grasp the concept of casting in SystemVerilog and have been tinkering with the following code: class packet; virtual function int compute_crc(); compute_crc = 12345; endfunction virtual task print; $display("This is a…

casting system-verilog

asked Sep 18 '15 at 06:21

je_pat

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1 answer

Aldec Riviera-PRO break simulation on SystemVerilog $error or $warning

Is is possible to configure Aldec Riviera-PRO simulator to break simulation on either $error or $warning SystemVerilog calls? If it is then how?

system-verilog

asked Sep 13 '15 at 16:29

kraigher

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2 answers

disable statement not killing other block in the fork statement

This is the code module aks(); initial begin rad temp ; temp = new; temp.fork_ll(); end endmodule //This is Class Which is used in above module class rad; task fork_ll(); fork begin:MYLOOP …

verilog system-verilog

asked Sep 09 '15 at 07:15

Akshay Patil

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