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Recently I've been coding an FFT module, and as you may think it requires a lot of wires. In order to simplify the code I'm trying to use packed arrays. But I got a problem in truncating and assigning. Suppose I have a 48-bit vector A, divided into 6 8-bit sub-fields:

logic [5:0][7:0] A;

Now, consider I have another vector B, which is 24-bit long, divided into 6 4-bit sub-fields:

logic [5:0][3:0] B;

Now the question is, how to assign the 4 MSB of each sub-field in A to the correspondent sub-field in B (preferably without using for loops)?

João
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Unfortunately, there is no special syntax in SystemVerilog to do this kind of lossy assignment in a single assignment.

dave_59
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  • Thank you dave_59. So in order to do that I used a for loop: always_comb begin for (int i=0;i<=1;i=i+1) B[i][3:0]=A[i][7:4]; end – João Oct 27 '15 at 17:41