Questions tagged [system-verilog]

SystemVerilog is a unified hardware design, specification, and verification language based on extensions to Verilog.

SystemVerilog is a unified hardware description language (hdl) and verification language. Its two primary uses are to describe logical circuits targeted towards field-programmable gate arrays (FPGAs - fpga), programmable logic devices (PLD) and application-specific integrated circuits (ASICs - asic) and to develop tests and environments to validate these circuit descriptions.

It is defined by IEEE 1800-2017 and with the exception of keywords, is a backwards-compatible superset of verilog, IEEE 1364-2005.

3298 questions

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Mixing nonblocking and blocking assignments in an always_ff block of an arbiter

I'm unable to wrap my head around Example 10-3 in SystemVerilog For Design book by Stuart Sutherland (and co.). See line 232 of : https://code.google.com/p/vak-opensource/source/browse/trunk/hardware/systemverilog/utopia-example/squat.sv?r=185 Here…

system-verilog fsm synthesis round-robin

asked Jun 13 '14 at 07:09

edc

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1 answer

Systemverilog dynamic casting issues

I've a code snippet like following in my testbench function void write_to_port( my_data_type_base data ); my_data_type_extended data_ext; if(!$cast(data_ext, data)); `uvm_error(get_type_name(), "failed to cast"); …

verilog system-verilog uvm

asked May 30 '14 at 22:51

newbie

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Casting struct to logic

This is related to my previous question. Consider the following module declaration: module DFF(d, q, CLK, RESET); parameter W = 2; input [W-1:0] d; input CLK; input RESET; output…

verilog system-verilog

asked May 28 '14 at 00:19

Ari

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Constraining an entire array in SystemVerilog based on another array

Is it possible to constraint an entire array in SystemVerilog to have the same value as another array? I tried this: class some_class; rand bit array1[10][10]; rand bit array2[10][10]; constraint arrays_c { array1 == array2; …

system-verilog constraint-programming

asked May 19 '14 at 08:04

Tudor Timi

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Passing string values to SystemVerilog parameter

I have a problem in passing a string value to a generic parameter in SystemVerilog. The modules are instantiated as shown below. The memory writes some values to FILE_OUT, which is a generic parameter. I need to produce two different files -…

verilog system-verilog

asked May 08 '14 at 23:06

dmm

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1 answer

Missing output on register file simulation

I'm trying to simulate a register file. My issues is that I am not getting an output for aData or bData. I suspect I have an issue with my assignments, but I'm not sure. My code for the module: `timescale 1ns / 1ps module registerfile( input [4:0]…

verilog system-verilog cpu-registers xilinx

asked May 06 '14 at 07:50

BlueSolrac

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How to properly cast arrays in SystemVerilog?

The bit-stream casting in SystemVerilog for arrays and structs does not seem very safe. For example, the following casting issue will only be caught at runtime (which could be hours into the simulation): bit [31:0] bit_queue[$]; logic [31:0]…

arrays casting system-verilog bitstream

asked Apr 24 '14 at 17:16

Victor Lyuboslavsky

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How to use verilog $deposit with indexes

How can $deposit be used when the path includes the index from the generate loop. When I try: for(int idx=0; idx<`NUM_OF_ENGIES; idx++) $deposit(i_engines_array.engines_loop[i].engine_top.soft_reset_n, 1'b0); I get the…

verilog system-verilog register-transfer-level

asked Apr 09 '14 at 10:04

Meir

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Fold-Unfold block of code / comment section in Emacs for UVM / SystemVerilog

I currently use emacs for UVM testbench environment development. I use verilog-mode with solarized theme. I like my current setup, however I would like to improve the functionality of emacs. I would like to add fold-unfold functionality for block…

emacs system-verilog uvm

asked Mar 30 '14 at 23:49

wisemonkey

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1 answer

SystemVerilog better way to copy a class

Which of the two copy functions are better? A. Using reference to a function parameter: function void copy(ref MyClass copyme); MyClass copyme = new this; endfunction B. Returning a newly instantiated copy: function MyClass copy(); return…

system-verilog

asked Mar 24 '14 at 01:59

e19293001

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Memory allocation in system verilog for dynamic array - new() / randomize() functions

I am having a class packet with a dynamic array. I would like to know if the new / randomize function of the class object can allocate memory for the dynamic array. class packet; rand int data[]; constraint c_data_size { data.size == 2; }; endclass…

memory-management verilog system-verilog

asked Mar 16 '14 at 17:50

Raghav

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How do I make use of multipliers to generate a simple adder?

I'm trying to synthesize an Altera circuit using as few logic elements as possible. Also, embedded multipliers do not count against logic elements, so I should be using them. So far the circuit looks correct in terms of functionality. However, the…

system-verilog synthesis

asked Mar 10 '14 at 15:16

geft

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2 answers

using assign statement for `define statement

I am using assign statement of verilog for assigning `define as below in my driver module. `define SPI_MASTER_P_IF spi_vif.spi_master_p.spi_master_p_cb `define SPI_MASTER_N_IF spi_vif.spi_master_n.spi_master_n_cb `define SPI_MASTER_IF class…

verilog system-verilog

asked Mar 05 '14 at 13:34

user3383729

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2 answers

SVA:Clock gating during SV assertion

I have an SV assertion which checks the property as below propert my_property; @(posedge clk) disable iff(reset) $rose(halt) ##0 ((rx_prio) > (expec_prio)) ##[0:$] $rose(rdy) |-> ##[1:100] (my_prio[rx_prio]==1'b1); endproperty:my_property I have…

verilog system-verilog assertion uvm system-verilog-assertions

asked Mar 04 '14 at 10:31

Suhas

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5 answers

Binary to Gray Conversion

module binarytogray #( parameter PTR=2 )( input logic [PTR:0] binary_value, output logic [PTR:0] gray_value ); genvar i; generate for(i=0;i

verilog system-verilog

asked Feb 20 '14 at 04:51

Vaibhav Sundriyal

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