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Questions tagged [system-verilog]

SystemVerilog is a unified hardware design, specification, and verification language based on extensions to Verilog.

SystemVerilog is a unified hardware description language () and verification language. Its two primary uses are to describe logical circuits targeted towards field-programmable gate arrays (FPGAs - ), programmable logic devices (PLD) and application-specific integrated circuits (ASICs - ) and to develop tests and environments to validate these circuit descriptions.

It is defined by IEEE 1800-2017 and with the exception of keywords, is a backwards-compatible superset of , IEEE 1364-2005.

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$size, $bits, verilog

What is the difference between $size and $bits operator in verilog.? if I've variables, [9:0]a,[6:0]b,[31:0]c. c <= [($size(a)+$size(b)-1]-:$bits(b)]; What will be the output at 'c' from the above expression?
Suhas
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How to create a string from a pre-processor macro

I have a preprocessor macro that represents a hierarchical path into my design. Example: `define HPATH top.chip.block I need to construct a string which holds the value of `HPATH, so in my example the string should equal top.chip.block. Is there a…
dwikle
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Modify verilog mode indentation

I am trying to have verilog mode indent everything using 2 spaces except decls and always. This is what I added to my .emacs: ;; `define are not indented …
igon
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Is the ++ operator in System Verilog blocking or non-blocking?

Good coding convention says that we should use blocking assignments in a combinational block, and non-blocking assignments in a sequential block. I want to use the ++ operator in a combinatorial block, but I don't know if it is blocking. So is…
nguthrie
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What SystemVerilog features should be avoided in synthesis?

SystemVerilog introduced some very useful constructs to improve coding style. However, as one of my coworkers always says, "You are not writing software, you are describing hardware." With that in mind, what features of the language should be…
nguthrie
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How can I use foreach and fork together to do something in parallel?

This question is not UVM specific but the example that I am working on is UVM related. I have an array of agents in my UVM environment and I would like to launch a sequence on all of them in parallel. If I do the below: foreach (env.agt[i]) begin …
Kaushal Modi
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Incrementing Multiple Genvars in Verilog Generate Statement

I'm trying to create a multi-stage comparator in verilog and I can't figure out how to increment multiple genvars in a single generate loop. I'm trying the following: genvar i,j; //Level 1 generate j=0; for (i=0;i<128;i=i+1) begin: level1Comp …
Adam
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Handling parameterization in SystemVerilog packages

SystemVerilog added packages to provide namespaces for common code pieces (functions, types, constants, etc). But since packages are not instantiated, they cannot be parameterized, so dealing with parameterized members is problematic. In practice…
JeffW
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How to set all the bits to be 0 in a two-dimensional array in Verilog?

I've built a 8*2bits array to represent a piece of memory in Verilog reg [1:0] m [0:7] There is a reset signal for this memory and if reset is 1, all the bits in this memory should be reset to 0. But I don't know how to set all the bits of m in a…
Michael
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What's the best way to tell if a bus contains a single x in Verilog?

I have a test bench that monitors a bus. Some of the signals (bits) within the bus can be 1'bx. For a variety of reasons, I need to know if any of the signals within the bus are 1'bx. What's the best way to test (not for synthesis -- only for…
Doov
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Difference between @(posedge Clk); a<= 1'b1; and @(posedge Clk) a<= 1'b1;

Is there any difference between @(posedge Clk); a<= 1'b1; and @(posedge Clk) a<= 1'b1; Note the semicolon after Clk. I came across similar lines of code when I was browsing through a testbench. I did some simple experiments and I could not…
Pulimon
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How to use const in verilog

Instead of using module ... ( .. ) ; #15 endmodule I want use module ... ( ... ) ; // GateDelay is a const, like in c language const int GateDelay = 15 ; # GateDelay endmodule Or same thing module ... ( ... ) ; // assume…
user478571
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Instantiate Modules in Generate For Loop in Verilog

I'm trying to instantiate some modules in Verilog using a generate block since I'm going to be instantiating a variable amount of them. genvar i; generate for (i=1; i<=10; i=i+1) begin status whatever_status ( .clk(clk), …
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How to use clock gating in RTL?

I am clock gating some latch and logic in my design. I don't have much experience in synthesis and place & route. What is the proper way to implement clock gating in RTL? Example1: always_comb begin gated_clk = clk &…
newbie
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What is the fastest way to perform hardware division of an integer by a fixed constant?

I have a 16 bit number which I want to divide by 100. Let's say it's 50000. The goal is to obtain 500. However, I am trying to avoid inferred dividers on my FPGA because they break timing requirements. The result does not have to be accurate; an…
geft
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