Precedence of chained unary operators in SVA assertions

Question

For a tool, I'm trying to correctly parse SystemVerilog assertions, and am confused about the correct precedence for certain expressions. The SystemVerilog standard has a nice table where they say that not > until > always for precedence. But I don't quite understand how this is supposed to work with alternations of the unary operators.

For instance, since not is higher precedence than until, we should obviously have:

    not r1 until r2   ---->   (not r1) until r2

And since until is higher precedence than always, we should obviously have:

    always r1 until r2   ---->  always (r1 until r2)

But what's the proper way to interpret the following?

    not always r1 until r2

I can imagine that two interpretations might be correct:

• not always (r1 until r2), since until binds more tightly than always, or
• (not always r1) until r2, since not binds more tightly than until

It looks like NCVerilog 15.10-p001 uses the first interpretation. Is there anywhere in the standard that discusses whether this is correct that I may have missed? It seems difficult to encode NCVerilog's precedence rules into a nice grammar...

Answer 1

Normally programming languages define unary operators as always having a higher priority than binary operators. In this case always is a unary operator with lower precedence than until, a binary operator.

Perl also has a similar situation, with the not operator (unary) having a lower precedence than && (binary). Conceptually, your expression is similar to the following Perl expression:

! not $r1 && $r2

If you try to evaluate this for all values of r1 and r1, you'll see that Perl interprets it as:

! not ($r1 && $r2)

This is conceptually the same interpretation as your simulator. Why it's like this I can't definitely say. I guess it's because interpretation 2 would violate until's precedence over always.