Wait for A Bit Change in Same Timestep in SV

Question

Here is the code

module m;
  bit x;

  initial
  begin
    fork
      begin
        wait(x == 1);
        wait(x == 0);
      end
      begin
        @(x == 1);
        @(x == 0);
      end
      #10 $display("Timeout");
    join_any
    disable fork;
  end

  initial
  begin
    #5;
    x = 1;
    // Some other Logical Stuff
    x = 0;;
  end     
endmodule

Now in this code, Timeout will happen, because x = 1 & x = 0 is done in the single time step.

One solution is to provide delay between x = 1 & x = 0, then both waits will work fine.

Is there any other method, which can work without providing hard-coded delays?

Note :- With events or semaphores like stuff, this problem can be solved. But I am looking for the answer in terms of coding style or methods, which can work without usage of events.

Im not entirely sure what you hope to achieve with this, I assume you dont know how long (in sim time) the other logic will take but you do want to know if it takes more than 10 time units. Also, you seem very concerned about memory for some reason, though you are willing to create two processes (a timer and the kill-timer forks) to achieve this. — Unn, Oct 01 '15 at 09:14
Another method to this would be to kill the timeout process using `disable` once your own tasks finish: `initial begin : watchdog #10 $display("Timeout"); end` with `disable watchdog` being the mechanism to kill the timer (put this where you want your `x <= 0;` to go in the current solution. — Unn, Oct 01 '15 at 09:15

H.Modh · Accepted Answer · 2015-10-01T07:22:33.923

2

There are several ways, which you can use here like event, semaphore, flag, etc. I have added an event in your code. Please find a modified code in below link.
http://www.edaplayground.com/x/Ws3

There are other ways also like,
1. Assign value "1" to x, during its declaration
E.g., bit x=1;
2. Use blocking and nonblocking assignment together in your 2nd initial block.
E.g.,

initial  
  begin  
    #5;  
    x = 1;  
    // Some other Logical Stuff  
    x <= 0; // Add non-blocking assignment  
  end   
end

=> The second option is not a good coding practice, but it'll solve your issue as both the assignment statments will work on different regions.

edited Oct 01 '15 at 07:22

answered Oct 01 '15 at 06:24

H.Modh

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Yes with events, we can do these. But that requires additional memory, whereas bit x is anyway used in the design. So is there any other coding style or method, which does not require additional thing, but still can work in the above case? – Karan Shah Oct 01 '15 at 06:34
You can also assign a value "1" to x, during its declaration, if it is okay with your logic. Please check the same link I have shared before. – H.Modh Oct 01 '15 at 06:45
Nope, because, though I have shown only one x = 1 & x = 0 cycle in the above sample code, in my actual code, x will be iteratively updated from x = 1 then x = 0 (In same time step), again after some time x = 1, x = 0 and so on. – Karan Shah Oct 01 '15 at 07:20
I have modified my answer again. Please check the second option in my answer. – H.Modh Oct 01 '15 at 07:23

Wait for A Bit Change in Same Timestep in SV

1 Answers1