Questions tagged [system-verilog]

SystemVerilog is a unified hardware design, specification, and verification language based on extensions to Verilog.

SystemVerilog is a unified hardware description language (hdl) and verification language. Its two primary uses are to describe logical circuits targeted towards field-programmable gate arrays (FPGAs - fpga), programmable logic devices (PLD) and application-specific integrated circuits (ASICs - asic) and to develop tests and environments to validate these circuit descriptions.

It is defined by IEEE 1800-2017 and with the exception of keywords, is a backwards-compatible superset of verilog, IEEE 1364-2005.

3298 questions

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Can Verilog/Systemverilog/VHDL be considered actor oriented programming languages?

These languages provide modules which are inherently concurrent and can handle asynchronous messages pretty neat (through ports). Keeping aside the fact that they cannot spawn module instances at runtime, do they qualify as actor based programming…

verilog actor system-verilog

asked Sep 17 '14 at 09:49

nav

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why I am not allowed to define unpacked array variable by 8'CC in system verilog?

I have tried with the below code: module try; int a[8]; initial begin a = 8'hCC; $display(a); end endmodule This is giving error as: Incompatible complex type assignment Type of source expression is incompatible with type of target expression. …

verilog system-verilog synopsys-vcs

asked Sep 16 '14 at 12:00

Megha Brahmbhatt

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1 answer

Generate block inside case statement in verilog or system verilog

Is there a way in Verilog or SystemVerilog to insert generate statement inside case statement to generate all the possible input combinations. For example a typical use case would be for a N:1 mux. case(sel) generate for(i = 0; i < N; i += 1) …

verilog system-verilog

asked Sep 15 '14 at 13:38

siu

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1 answer

How do I fix "Error-[IBLHS-NT] Illegal behavioral left hand side"?

I am trying to debug this code shown below. I can not get it to work at all. The attached Verilog file has two modues: 1) "equality" which defines the Device Under Test (DUT) and 2) "test" which generates the inputs to test the DUT. The module…

verilog system-verilog

asked Sep 08 '14 at 23:57

codewarrior453

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1 answer

missing complete candidate for verilog-mode with company-mode

I am using company-mode to do the auto complete in Verilog-mode. I want to write end and start a newline. But after I key in end, company-mode gives me the candidate list(endfunction, endclass, endmodule, endpackage). I have to put an extra SPACE…

emacs elisp verilog system-verilog

asked Aug 27 '14 at 00:34

Enze Chi

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image file reading in system verilog

I have written system verilog code for reading data from an image file (800*600 - *.raw). The file actually contains 800 * 600 * 3 bytes. But my code can only read upto almost half the data. After that the read data seems to be…

system-verilog

asked Aug 20 '14 at 09:08

surfing_alien

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0 answers

Viewing enum names in vcs ucli

I am working in VCS UCLI (ie, the command line interface) and am having trouble getting VCS to display various state variables, of a typedef'd enum type, value as the name rather than the number. For example, I have some SystemVerilog like…

enums verilog system-verilog synopsys-vcs

asked Aug 18 '14 at 21:41

Unn

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SVA - Is there any way to check an variable variable pattern in a variable length serial output using system verilog assertion?

For example, I have a pattern pt=1101 that needs to be checked in a serial output s_out= 1011101110111011 (LSB first). I am trying to check the "pt" in "s_out" only using SVA without using always block. Note: pt and s_out both are variable in…

system-verilog system-verilog-assertions

asked Aug 12 '14 at 18:34

susun

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2 answers

Calling ModelSim commands from SystemVerilog

Is there a way to call a ModelSim command (e.g. force -freeze) from SystemVerilog?

system-verilog modelsim

asked Aug 12 '14 at 12:00

Andy

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1 answer

$sscanf : Invalid format specifier '

I'm trying to port a rather big testbench from VCS to QuestaSim, and while everything works in VCS, there are some problems when porting it. The latest error I get when running vsim is $sscanf: Invalid format specifier '. It fails at two places in…

verilog system-verilog modelsim

asked Jul 28 '14 at 11:41

trippelganger

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1 answer

SystemVerilog: how to assert the signals internal to module?

I am pretty new to Verilog (and of course with SystemVerilog as well). I have a RTL module to test its functionality. I was trying to use assertion to do that, instead of applying stimulus then observing it, so that my module can be reused.. So…

system-verilog assertion system-verilog-assertions

asked Jul 25 '14 at 16:16

user3655233

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2 answers

Convert unsigned int to Time in System-verilog

I have in large part of my System-Verilog code used parameters to define different waiting times such as: int unsigned HALF_SPI_CLOCK = ((SYSTEM_CLK_PERIOD/2)*DIVISION_FACTOR); //DEFINES THE TIME Now since I define a timescale in my files I can…

system-verilog

asked Jul 21 '14 at 11:18

Theo

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2 answers

UVM: Driving clock through interface

I'd like to be able to control the clock/data pair on a UVC interface. Controlling data is relatively straight-forward. Where I am getting wrapped around the axel is with the clock. How can I control the clock in the interface such that it can be…

system-verilog uvm

asked Jun 25 '14 at 21:47

user3111358

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2 answers

How to write a Verilog function that determines if all elements in an array are equal?

Let's say I have N registers and I want a function that checks if all register contents are equal. How do I write that without having to spell out every single element? function equal (input [0:N-1][width-1:0] in); equal = (???) ? 1'b1 :…

verilog system-verilog

asked Jun 18 '14 at 13:32

geft

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3 answers

Warning when setting uvm_reg values through a task

I am creating a framework where my verification team and I can write uvm test cases with ease. The basic idea is that my base (uvm_)sequence only contains the one line in its body task: regs.update(status); From my individual (uvm_)tests, I can set…

system-verilog uvm

asked Jun 16 '14 at 17:26

noobuntu

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