Questions tagged [system-verilog]

SystemVerilog is a unified hardware design, specification, and verification language based on extensions to Verilog.

SystemVerilog is a unified hardware description language (hdl) and verification language. Its two primary uses are to describe logical circuits targeted towards field-programmable gate arrays (FPGAs - fpga), programmable logic devices (PLD) and application-specific integrated circuits (ASICs - asic) and to develop tests and environments to validate these circuit descriptions.

It is defined by IEEE 1800-2017 and with the exception of keywords, is a backwards-compatible superset of verilog, IEEE 1364-2005.

3298 questions

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How to pass parameterized class to a module instance?

include "cls.sv" module top(); int x; spl_cls #(10) o_spl_cls; /*Code Continues, here o_spl_cls object has been created using new();*/ dummy i_dummy(o_spl_cls); //I instantiated another module and passed …

system-verilog

asked Jan 12 '16 at 13:34

Akshay Patil

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1 answer

SystemVerilog: Creating packed arrays using variables

I would like to create a task that does the following in SystemVerilog: Receive the 3 input parameters and 1 output parameter. Randomizes a data and assign the data to a bit variable (output parameter). 1. task rand_wr_data(input int size, int…

arrays task system-verilog

asked Dec 23 '15 at 14:37

user3531168

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1 answer

Forcing a member of a struct

I am trying to force some internal nodes in my design. One thing I am trying to force is a member of a struct. When I try to do this: module struct_force; struct { logic a; logic b; logic c;} d; initial begin force…

system-verilog

asked Dec 15 '15 at 20:48

nguthrie

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Adding header files in Verilog

I wanted to add a header file to my Verilog project. This should be a very easy thing to do. However, it turns out is is not trivial. This my header file. Let's say the file name is parameters.vh `ifndef _parameters_vh_ `define…

verilog system-verilog intel-fpga

asked Dec 12 '15 at 12:04

MTMD

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Can I use an array 'arr[x][y]' inside an always block? Is it Synthesizable?

always@(posedge clk) begin r00<=r01; r01<=r02; r02<=arr[x][y]; //code end will this be synthesizable inside a generate block? Also that 'arr' is 2-Dimensional.

system-verilog synthesis

asked Dec 12 '15 at 07:04

Joe

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2 answers

UVM sequences producing related numbers

In the UVM test I declare and start the sequences, but the output from separate sequences with the same parameters are "related" somehow(see example at the bottom), so when I do cross coverage I only coverage 12.5% of the cases, what is causing…

system-verilog verification uvm

asked Dec 09 '15 at 10:38

StanOverflow

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1 answer

Array as module parameter

How to pass a constant array as a module parameter? I want to build a shift register width different shift widths. The possible shift widths should be definable via a module parameter. I tried something like the following, but this not…

verilog system-verilog hdl

asked Dec 01 '15 at 18:14

Razer

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Gate Cost of 16 bit Ripple carry adder, and 16 bit (Two Level) Carry Look Ahead Adder

Hi i was just curious what would be the gate cost of combinational 16 bit Ripple carry adder, and 16 bit (Two Level) Carry Look Ahead Adder. Thanks

verilog system-verilog circuit circuit-diagram iverilog

asked Nov 24 '15 at 00:09

jake

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0 answers

running/ compiling system verilog snippets(not an entire set of testbench verification codes) on windows

I am trying to compile and run small snippets of systemverilog on windows. I am trying to do that in powershell. Is there any way, I can do that ?

powershell system-verilog

asked Nov 20 '15 at 16:55

raiyyan09

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1 answer

Systemverilog breakout array of interfaces

I have a lower level module that implements an array of interfaces. At a higher level I would like to break out that interface array and assign it to individual ports (the code is just an example . . . no special functionality intended). //…

arrays system-verilog

asked Nov 19 '15 at 21:39

user4061565

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2 answers

Can we can have print statement in classes without any function/task in system verilog

Can we can have print statement in classes without any function/task in SystemVerilog? http://www.edaplayground.com/x/8Y8 class A; int x=10; $display("x=%d",x); endclass module abc; A a; initial begin a=new(); end endmodule

system-verilog

asked Nov 12 '15 at 14:42

ranadheer chinthalapalli

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2 answers

how to get the number of elements in an array in systemverilog?

I'm new to systemverilog; I need to run over the elements of an array that I don't know its size. I need to read 2 elements in each iteration so I cant use foreach (can I ? ). I need to do something like that : for(int i = 0 ; i < arraySize ; i+=2…

arrays for-loop methods system-verilog

asked Nov 11 '15 at 15:30

Adi

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3 answers

wire in always block/case statement - Verilog

Following is a sample code that uses case statement and always @(*) block. I don't get how the always block is triggered and why it works even when x is declared as wire. wire [2:0] x = 0; always @(*) begin case (1'b1) x[0]: $display("Bit 0 :…

case verilog system-verilog

asked Nov 07 '15 at 05:31

rahulcodesinverilog

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0 answers

SystemVerilog to VHDL std_logic generic

My problem is that I have to pass a generic from a SystemVerilog module to a VHDL entity of type std_logic, that will be directly used inside that entity in signal assignments. entity foo is generic( my_generic : std_logic); port (...); end…

generics vhdl system-verilog modelsim xilinx-ise

asked Nov 05 '15 at 10:29

arandomuser

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1 answer

Initialization priority in verilog

Hello verilog experts, In the verilog code below, can I be 100% that top.test.p will be systematically initialized to 200? Or will I have a race between the variable initialization and the initial statement? In other words, some simulators will…

verilog system-verilog

asked Nov 02 '15 at 23:26

user3352256

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