system verilog : Overridden members system verilog classes

Question

class my_a;
int member1 = 1;
endclass
class my_ea extends my_a;
int member1 = 2;
endclass

Now when I do

my_a A;
my_ea EA;
EA =new();
A=EA;

EA = new(); has given handle to object of type my_ea to class variable EA. A=EA; passes the same handle (pointer value which points to object of my_ea) to A. So, A.member1 should refer to value 2. But it refers to value 1. Why?

Answer 1

So far, System-Verilog does not allow overriding of class variables. Only virtual methods can be overridden.

There is nothing like virtual for class members, so parent class can never directly access them. When using class_object.member, the particular class is referred to. Henceforth, this is not possible.

Answer 2

You cannot redefine an existing member by extending a class. You should use virtual methods to access (get/set) them. For instance, I added "get_member1" function to your code, and it returns 2 when called from a base class handle as you wanted.

class my_a;
  int member1 = 1;
  virtual function int get_member1();
    return member1;
  endfunction
endclass

class my_ea extends my_a;
  int member1 = 2;
  virtual function int get_member1();
    return member1;
  endfunction
endclass

module tb;
  initial begin
    my_a A;
    my_ea EA;
    EA =new();
    A=EA;
    $display("%0d", A.get_member1());
  end
endmodule

You can similarly define "set_member1(int value)" function and use it to change its value.

Answer 3

In your case A.member1 should return the original member of its own class. When you are overriding a class members, you are basically hiding the overridden members. Super/base class can never access overridden member in its subclass.

As far as I know, only method identified with virtual, randomize() function and class constraint can be overridden without hiding them from the base class - thus they allow base class to reference to them (polymorphism)

For more info, please find here IEEE 1800-2012 in section 8.14 Overridden members.