I'm trying to grasp the concept of casting in SystemVerilog and have been tinkering with the following code:
class packet;
virtual function int compute_crc();
compute_crc = 12345;
endfunction
virtual task print;
$display("This is a packet");
endtask
endclass: packet
class bad_packet extends packet;
function int compute_crc();
compute_crc = 54321;
endfunction
task print;
$display("This is a bad packet");
endtask
task print2;
$display("This is not accessible from base");
endtask
endclass: bad_packet
module test;
packet pkt;
bad_packet b_pkt;
initial begin
b_pkt = new();
pkt = b_pkt;
$cast(b_pkt, pkt);
b_pkt.print;
pkt.print;
end
endmodule
I have a base class 'packet', and a derived class 'bad_packet'. By using $cast, will I be able to access bad_packet's method print2? Are there other ways of doing this? Thanks!