Is is possible to configure Aldec Riviera-PRO simulator to break simulation on either $error
or $warning
SystemVerilog calls? If it is then how?
Asked
Active
Viewed 273 times
1

kraigher
- 629
- 4
- 9
1 Answers
1
I don't think there's a specific config option for promoting $error
or $warning
to a breakpoint in Riviera-PRO, although it worth checking with their support. You do have a couple of options:
- Replace
$error
with$fatal
- Write a VPI module to overload the system tasks with custom C code
The second option would look something like this:
#include "vpi_user.h"
// System function overload on $warning and $error to stop sim
static int system_function_overload(char *userdata)
{
vpiHandle systfref, args_iter, argh;
struct t_vpi_value argval;
const char *msg = "*** NO MESSAGE PROVIDED ***";
// Obtain a handle to the argument list
systfref = vpi_handle(vpiSysTfCall, NULL);
args_iter = vpi_iterate(vpiArgument, systfref);
// Pull out the string passed in as the first argument
if (args_iter) {
argh = vpi_scan(args_iter);
argval.format = vpiStringVal;
vpi_get_value(argh, &argval);
vpi_free_object(args_iter);
msg = argval.value.str;
}
vpi_printf("BREAK sim from %s:%d with msg %s\n",
vpi_get_str(vpiFile, systfref),
vpi_get(vpiLineNo, systfref),
msg);
vpi_control(vpiStop);
return 0;
}
static void register_system_functions(void)
{
s_vpi_systf_data tfData = { vpiSysTask, vpiSysTask };
tfData.sizetf = NULL;
tfData.compiletf = system_function_compiletf;
tfData.calltf = system_function_overload;
tfData.user_data = NULL;
tfData.tfname = "$warning";
vpi_register_systf( &tfData );
tfData.tfname = "$error";
vpi_register_systf( &tfData );
}
void (*vlog_startup_routines[])(void) = {
register_system_functions,
0
};

Chiggs
- 2,824
- 21
- 31
-
Custom C is unfortunately not an alternative for my needs as I do not want C compilation or compilers in my tool flow just for this feature. I guess I have to use fatal. To bad, in Modelsim it was possible to achieve this. – kraigher Sep 15 '15 at 16:03
-
@kraigher Riviera-PRO ships with a compiler, so you can enable VPI with `ccomp -pli -o myvpi.so my_vpi_file.c` and `asim -pli myvpi.so toplevel` in the TCL script that compiles your design. – Chiggs Sep 15 '15 at 16:07
-
I will consider using it but I have to think about the consequences. If the compiler ships with the tool as you say at least this solution does not impose any extra tools to the flow. I am actually in the process of adding SystemVerilog support to the VUnit VHDL test automation framework which I am one of the authors of. One of the design decisions I face is if I should support break on error by default and optional break on warning as we do for VHDL. – kraigher Sep 15 '15 at 16:18