Questions tagged [system-verilog]

SystemVerilog is a unified hardware design, specification, and verification language based on extensions to Verilog.

SystemVerilog is a unified hardware description language (hdl) and verification language. Its two primary uses are to describe logical circuits targeted towards field-programmable gate arrays (FPGAs - fpga), programmable logic devices (PLD) and application-specific integrated circuits (ASICs - asic) and to develop tests and environments to validate these circuit descriptions.

It is defined by IEEE 1800-2017 and with the exception of keywords, is a backwards-compatible superset of verilog, IEEE 1364-2005.

3298 questions

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SystemVerilog parameterized functions in Quartus II

I have the following code, file c.sv: virtual class C#(parameter W = 32); // line #2 where error message points static function logic [W-1 : 0] f(input logic [W-1 : 0] in); return ~in; endfunction endclass I then call it from…

system-verilog quartus

asked Sep 09 '15 at 06:40

Mishka

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1 answer

Slicing array of struct in SystemVerilog

Suppose there is a structure declared as: typedef logic [7:0] Data; typedef struct packed { logic valid; Data data; } MyStruct; An array of the struct is declared as: MyStruct foo [8]; Is there a way other than using for loop to extract a…

system-verilog

asked Sep 09 '15 at 01:18

ohcamel

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Verilog generate statement with always@(*) block

I have this generate block below which I think should work, but I am seeing issues with the always @(*) part under the else block. When using VCS, temp_in[i+1][j] is assigned 'x' always. I expect it to be set to '0'. If I instantiate a module/gate…

verilog system-verilog

asked Aug 28 '15 at 21:34

Wilderness

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Conditional increment in generate block

I want to create 256 instances of foo. Therefore, I have two nested generate loops. However, I need a separate index variable l to for a proper selection of the signal. genvar j, i, l; generate l = 0; for(j = 0; j < 16; j++) begin for(i =…

verilog system-verilog hdl

asked Aug 20 '15 at 16:27

Razer

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Include a Verilog Header file using a Do file for Modelsim

In a system-verilog file that I was given is an include for a Verilog Header file (.vh). When I manually run a simulation in Modelsim I usually go into the properties of the file ("Verilog & SystemVerilog" tab) and include the directory that holds…

verilog simulation header-files system-verilog modelsim

asked Aug 20 '15 at 09:57

Marmstrong

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SystemVerilog generic multiplexer

I am trying to come up with a way to define a synthesizable generic multiplexer (either as a function or module) that can be used with wires, and typedefs (enums, structs) in SystemVerilog Is that possible in any way? If not, what would be the…

system-verilog hdl

asked Aug 19 '15 at 11:17

Sébastien Baillou

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1 answer

Explicit cross coverage definition

1.Is it possible to explicitly list cross coverpoints in system verilog ? Something like below.. 2.Since I am only interested in the occurrences of doublets {{1,2},{3,1},{2,4}} and not b1or b2 standalone, can I accomplish this without creating…

verilog system-verilog uvm

asked Aug 14 '15 at 17:25

Jean

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Loading different files with $readmemh to the same memory in a automated loop?

I'm generating frames from a video file, which I then read from my testbench. What I'm doing so far is to load the same memory "mem" with different memory image file every time the task is called, which works perfectly fine: task play_frame(input…

verilog system-verilog

asked Aug 13 '15 at 13:54

Goled

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Get the element in front of a specified pattern in tcl

I am writing a script that will search a system Verilog testbench and pul out the modules and then search the modules hierarchy until it reaches the very bottom of the chain. Is there any way to search for a pattern, and then take the element that…

pattern-matching tcl system-verilog

asked Aug 11 '15 at 13:36

Liam P

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2 answers

Can a thread re-start without being killed in systemverilog fork-join/join_any disable fork setup?

I have a very simple piece of code that is boggling my mind. ->ev1; //Trigger the event of interest fork : main_fork begin : T1 $display("T1 is RUNNING"); fork begin $display("T1.B3 is RUNNING"); $display("T1.B3…

multithreading join fork system-verilog

asked Aug 09 '15 at 15:10

user3662733

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1 answer

Monitoring a member of an associative array

I have an associative array called array, on which I'm trying to do the following: initial begin $monitor ("array[10]=%h", array[32'h20]); end I need to know whenever there is a change on this member. But I get the following error: Associative…

verilog system-verilog

asked Aug 06 '15 at 22:32

Ari

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Unexpected Nonexistent Associative Array Warning in Questa after rollover

Normally in Associative Array, Rollover issue is taken care by the tool. But in QuestaSIM, I am facing the issue, like if key of the Associative Array is 64 bit variable, then after overflow, it does not store data properly. Suppose index is…

system-verilog questasim

asked Aug 04 '15 at 13:54

Karan Shah

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Systemverilog - multiple process triggering same event

Why am I getting the result shown below? I would expect that multiple trigger to the update_ev event should cause the display "Main Loop ,.." to be executed twice. But it is only executed once. program multiple_trigger(); initial begin event…

system-verilog

asked Jul 21 '15 at 13:08

Kanishk Sugand

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3 answers

Randomize dut parameters in system verilog

I am writing a test bench in system verilog for a dut, and in the field it is possible for the parameter DEPTH to change and so I have been trying to figure out how to randomize a parameter. It is currently set at 20 but it has a range of 7 to 255.…

random parameters system-verilog hdl

asked Jul 20 '15 at 18:12

Liam P

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1 answer

Concatenated vector is truncated in synthesis

In attempting to concatenate a 32-bit floating point vector for a linear function shift register all goes well in behavioral simulation. However, in post-synthesis the "random_float" net has been truncated to 31 bits. It seems the "sign" is getting…

verilog fpga system-verilog vivado

asked Jul 16 '15 at 19:29

jwanga

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