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Questions tagged [system-verilog]

SystemVerilog is a unified hardware design, specification, and verification language based on extensions to Verilog.

SystemVerilog is a unified hardware description language () and verification language. Its two primary uses are to describe logical circuits targeted towards field-programmable gate arrays (FPGAs - ), programmable logic devices (PLD) and application-specific integrated circuits (ASICs - ) and to develop tests and environments to validate these circuit descriptions.

It is defined by IEEE 1800-2017 and with the exception of keywords, is a backwards-compatible superset of , IEEE 1364-2005.

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Best way to access the uvm_config_db from the testbench?

I want to create a clock in my top level testbench whose period can be controlled from the test. What I did was set the period into the uvm_config_db and get it back in the testbench. I had to put in a #1 to make sure that the build phase was…
nguthrie
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proper use of "disable fork" in systemverilog

I've something similar to following pseudo code: for (lets say 10 iterations) begin // Do some configuration changes fork begin ///apply input to design end begin while (1) /// at particular point…
wisemonkey
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What is the benefit of automatic variables?

I'm looking for benefits of "automatic" in Systemverilog. I have been seeing the "automatic" factorial example. But I can't get though them. Does anyone know why we use "automatic"?
bang
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Can Verilog variables be given local scope to an always block?

I sometimes find it useful to use blocking assignments for "local variables" inside clocked always blocks. This can help cut down on repeated code. To avoid accidentally using the same variable in a different always block (which can be…
mksuth
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How can I separate long statements into lines in Verilog

For example, I have a single long statement: $display("input_data: %x, output_data: %x, result: %x", input_data, output_data, result); How can I make it into single…
e19293001
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What's included in a Verilog always @* sensitivity list?

I'm a bit confused about what is considered an input when you use the wildcard @* in an always block sensitivity list. For instance, in the following example, which signals are interpreted as inputs that cause the always block to be…
Frank Dejay
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Printing signed integer value stored in a variable of type reg

How do I print a signed integer value stored in an 8-bit register declared as: reg [7:0] acc; Using: $display("acc : %d", acc) It prints the unsigned value. What's the correct syntax for the $display function?
Nullpoet
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Error: "(vlog-2110) Illegal reference to net"

I have a simple FIFO code in SystemVerilog. I get several vlog-2110 illegal reference to net error messages. My error messages are followed by my code. Error messages: vlog -work work -sv -stats=none C:/Users/Single_FIFO.sv Model Technology…
SSadh
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Width independent functions

Is it possible to write a function that can detect the input data width automatically? For example, consider the parity function below: function parity; input [31:0] data; parity = ^ data; endfunction When parity(data) is called, the input…
Ari
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SystemVerilog passing functions as an argument

Is it possible to pass a function as an argument in SystemVerilog? This code hopefully demonstrates though it doesn't work. Any help? Thanks. module funcparam; int result; function int xxx(int x, ref fun); …
e19293001
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Verilog Always block using (*) symbol

I have a simple question regarding how to write an always block in a Verilog module. If I have the following inputs in my Verilog module: input [31:0] PCplus4 ; // Value of PC + 4 input [31:0] A; // Value A, i.e.…
all_by_grace
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why should I use unpacked vectors in System Verilog?

Following up on this question about the difference between packed and unpacked vectors in SV, why would I ever want to use unpacked vectors? Packed vectors have these advantages that unpacked vectors don't have: You can perform bit-wise operations…
Nathan Fellman
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In SystemVerilog, is it allowed to read a parameter from an interface

I am a bit confused as to if it is legal, from a standards stand point, to read a parameter from an interface. Like so interface foo_if #(parameter BAR=5)(); ... logic [BAR-1:0] data; modport slave(input data, ...); endinterface module…
AxelOmega
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Passing parameters to Verilog modules

I am in the process of writing some Verilog modules for an FPGA design. I looked around the internet to find out how I best parametrize my modules. I see two different methods occurring often. I included an example hereunder of the two different…
eavsteen
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Connecting hierarchical modules: struct vs interface in SystemVerilog

In SystemVerilog hierarchical modules can be connected by simple data types, complex data types (structs, unions, etc), or interfaces. The feature that I am interested in is aggregating all signals between two modules in one place which simplifies…
Ari
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