Randomly Map Bits in Verilog

Question

I am trying to create a simple, synthesizable module that randomly maps bits of an output to bits of the input without duplicates. For example, something like this for 8-bit in/out:

module Scrambler(in, out);
    parameter WIDTH = 8;

    input wire [WIDTH-1:0] in;
    output wire [WIDTH-1:0] out;

    assign out[0] = in[6];
    assign out[1] = in[5];
    assign out[2] = in[3];
    assign out[3] = in[7];
    assign out[4] = in[1];
    assign out[5] = in[4];
    assign out[6] = in[0];
    assign out[7] = in[2];
endmodule

I want to replace the series of assign statements with a generate block so the width of the input/output can be fully parameterized. I just cannot think of a way to create a cyclic series of random values only at synthesis time. The mapping will never need to change after synthesis.

Thanks for any help!

toolic · Answer 1 · 2020-06-19T14:34:54.810

Wrong tool for the job, like trying to drive a nail with the butt of a screwdriver. Use a hammer, like these few lines of Perl (or a hammer of your own choosing):

use List::Util qw(shuffle);
my $n = shift() - 1;
my @arr = shuffle(0 .. $n);
print "assign out[$_] = in[$arr[$_]];\n" for 0 .. $n;

We all use auto-generated Verilog code. This is no different. Just copy'n'paste the output into your Verilog file.

Randomly Map Bits in Verilog

1 Answers1