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  • Say we have a SystemC model of decade counter and I want to verify SystemVerilog Counter RTL using SystemC model. How can we connect these two in SV/UVM based testbench so as to communicate between them.
MayurKubavat
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  • SystemVerilog provides Direct Programming Interface (DPI) for communicating with various other languages. For more information on SystemC DPI, [this](http://1sutherland.com/papers/2004-SNUG-Europe-paper_SystemVerilog_DPI_with_SystemC.pdf) pdf may be helpful. – sharvil111 Nov 02 '15 at 09:04
  • Thanks sharvil... Looks helpful. I'll try it out. – MayurKubavat Nov 03 '15 at 10:28
  • Many modern commercial simulators that ship with Verilog/SystemC support should be able to do co-simulation. However, the tool commands and instructions vary and depend on what simulation tool you are using. Please check your simulator manuals. – jclin Nov 05 '15 at 19:35

2 Answers2

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Mentor developed a free package called UVMConnect that was developed specifically for the application you are asking about. See https://verificationacademy.com/topics/verification-methodology/uvm-connect. You will need a simulator that supports SystemVerilog and SystemC simulating together, like Questa.

dave_59
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If you're using QuestaSim I think UVM-connect from Mentor is the way to go. When I first used it(4 years ago) it was very buggy and gave the most cryptic segfault errors I've ever seen. But, with help from the Mentor support I managed to overcome them and get stuff done. It should be more stable now, but if you have problems with it don't hesitate to contact Mentor support. They are very responsive.

However, if you're using Cadence tools and/or the e language I think that UVM-ML from Cadence is a much more comprehensive solution. It allows you to connect components written in any combination of languages(SV-SC, SV-e, SC-e) and it has nicer documentation and examples. I understand it's also compatible with all simulators now. You can find it here : http://forums.accellera.org/files/file/65-uvm-ml-open-architecture/

Not sure what Synopsis folks recommend for their tool suite. Maybe someone who used them can offer more information on this. But I'm guessing that both UVM-ML and UVM-Connect could work since their makers claim that they are portable.

And lastly, if you're planning to use SystemC as a verification language(very unlikely but just for the sake of diversity) there is something called UVM-SystemC which is basically a clone of SV-UVM written in C++/SystemC. It's currently in its alpha release and it lacks many features(register modeling, constrained randomization, coverage collection, etc.). It feels a lot like SV-UVM and I think it's a nice toy to play with in your spare time if you can't afford a commercial simulator license. You can find it here http://accellera.org/images/downloads/drafts-review/uvm-systemc-1.0-alpha1.tar.gz

Tiberius P.
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