Systemverilog breakout array of interfaces

Question

I have a lower level module that implements an array of interfaces. At a higher level I would like to break out that interface array and assign it to individual ports (the code is just an example . . . no special functionality intended).

// -------- INTERFACE --------
interface my_if;
    logic   d;
endinterface

// -------- INTERMEDIATE MODULE --------
module intermediate(
    my_if   i1,
    my_if   i2
    );

    sub mySub(
        .a   ('{i1,i2}),
        .w1  (1'b1)
    );
endmodule

// -------- SUB MODULE --------
module sub(
    my_if         a[2],
    input wire    w1
    );

    assign a[0].d = w1;
    assign a[1].d = ~w1;
endmodule

The above code gives me an error:

The interface port 'a' of module 'sub' whose type is interface 'my_if' is illegally connected.

Two questions:

how can I implement the above?
how do I assign an interface to another of the same type? ie in the code above I tried assigning and aliasing the array interface to an intermediate one (alias i1 = ii[0]) . . . but I can't figure out how to do that.

score 1 · Accepted Answer · answered Nov 19 '15 at 22:01

1

This is not allowed in SystemVerilog. There is a real problem with interfaces in that you cannot compose one interface from a collection of other interfaces.

The only workaround is using assign statements that would connect the signals in an individual interface ports to the signals in the array of interface signals.

You would be better of not using interface and perhaps use a struct instead.

answered Nov 19 '15 at 22:01

dave_59

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I am not sure I am following . . . I am not trying to compose an interface from a collection of other interfaces. I am just trying to assign an individual interface from an array of interfaces to one of the module ports. I have done something similar going from one instance with an array of interfaces to multiple instances with a single interface each (just assigning them a[0], a[1], etc). The problem I am having is assigning one whole interface from an array to a single interface port of the module. – user4061565 Nov 19 '15 at 22:09
You are composing. You are trying to bring together individual interface instances at a higher module level together to form a single instance of an array of interfaces at a lower level. The syntax you tried to use was a concatenation - which is a compositional operator. There is nothing like that for interfaces. – dave_59 Nov 19 '15 at 23:50
1

Wow . . . thanks . . . this seems to be a pretty big omission, reducing the usefulness of interfaces. There really seem to be two main items lacking: (1) a way to combine interfaces into arrays (one can decompose an array of interfaces, but not the other way around); (2) assign an interfaces to another interface of the same type, and maybe opposite ports, to connect them together (an anecdote would be an extension cord). – user4061565 Nov 20 '15 at 02:08
Interesting I was trying to do the same thing. Hardware languages are still far behind software languages... Composition is quite basic. – Alexis Aug 12 '19 at 12:21

Systemverilog breakout array of interfaces

1 Answers1