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Questions tagged [system-verilog]

SystemVerilog is a unified hardware design, specification, and verification language based on extensions to Verilog.

SystemVerilog is a unified hardware description language () and verification language. Its two primary uses are to describe logical circuits targeted towards field-programmable gate arrays (FPGAs - ), programmable logic devices (PLD) and application-specific integrated circuits (ASICs - ) and to develop tests and environments to validate these circuit descriptions.

It is defined by IEEE 1800-2017 and with the exception of keywords, is a backwards-compatible superset of , IEEE 1364-2005.

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How to create systemVerilog wrapper for vhdl DUT?

This is simple VHDL design for flipflop. Please show me how to import vhdl file to systemverilog so i can do verification using UVM. If there is better way then wrapper please tell me. I am using Questa 10.4d. library ieee; use ieee.…
Sanjin Arsenovic
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assertion for holding the reset for a long time

I see that assertions are always related to n number of cycles of a clock. Is there any way I can check the duration wrt timescale? Meaning let's say I want to check if a reset is hold for 100ns or less, how do we write a assert statement for this?
crazydesi
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Decode name of packed struct member based on bit position

I have a register map which is generated with a script. The output of the module is one huge packed struct. This is normally not a problem, but when I lint my code I get warnings like this: *W,UNCONO (./module_name.v,158):: 'reg[1415]' is not…
nguthrie
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How to handle SystemVerilog-specific types in c and vice-versa?

As I know, in systemverilog, there are no char type and string. SystemVerilog-specific types, including packed types (arrays, structures, unions), 2-state or 4-state, which have no natural correspondence in C. if we use the char or string in c, How…
sogood
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Write one byte at a time to a binary file in SystemVerilog

I want to write a binary file (meaning that it needs to be opened in a hex editor). I want to write one byte at a time in SystemVerilog. I currently am only able to write 32-bits (4 bytes) at a time. This does not work for me. Here's the code…
Russell
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can you compare an int to a bus in verilog?

I know this is probably trivial, but this is the umpteenth time I've googled it so I'd like to get a definitive answer. I have the following code in a testbench, so it need not be synthesizable. Will this comparison work as expected? logic [4:0]…
mtveezy
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How do I assign one multidimensional array to another in system verilog

In System Verilog, I have: wire [2:0][1:0] sig1; wire [2:0][3:0] sig2; I'm attempting to do: assign sig1[2:0][1:0] = sig2[2:0][1:0]; NCVerilog tells me: assign sig1[2:0][3:0] = sig2[2:0][3:0]; | ncvlog: *E,MISEXX…
jkang
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How to initialise a register to a random value in verilog?

I am using a clock toggle circuit in the design. Here is the behavioural model of the cell. module toggle (En, CP, Q); input CP, En ; output Q; reg Q_int; `ifdef INIT initial Q_int = 1'b0; `endif always @ (posedge CP) begin …
Neela Lohith
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How to change ordered port list into named port list in systemverilog?

Now I'm trying to implement systemverilog tutorial here, Especially, I am referring the switch tutorial of SystemVerilog. If you view the code, they are used ordered port list in testcase TC(mem_intf, input_intf, output_intf[4]); but I want to…
user5523035
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Syntax error in verilog

I have about six errors but they are all the same. The error goes as such: near "?": syntax error, unexpected '?' I've been trying to figure out how to fix this and I've looked at other problems in stackoverflow relating to this problem but to no…
Luis Averhoff
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Declaration of a Verilog function in a header file

When I try to compile a testbench which includes a header file which contains a function declaration Icarus Verilog (v10.0 stable) aborts with the following error: mpeg.vh:133: error: function declarations must be contained within a module. This…
andrsmllr
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What is the purpose the 'new' and 'virtual' in systemverilog?

I'm trying to learn about SystemVerilog. While reading about it, I came across the following code, which I cannot fully understand: Test1. class A ;  task disp(); $display(" This is class A ");  endtask  endclass  class EA extends A ;  …
bural
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Verilog Testbench Errors for Comparator

I'm new to Verilog and I need to make an 8-bit comparator for when a is equal, less than, and greater than b. Here's what I have for the code (which gives me no errors): module MagnitudeComparator8bit (input signed [7:0]a, …
smd
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How to allocate contiguous memory for dynamic multidimensional arrays in SystemVerilog?

Is there a way in SystemVerilog to create a dynamic array that allocates its memory contiguously? I'm trying to read in data from a file into a dynamic array. The problem appears to be that the dynamic array is not in contiguous memory locations,…
Russell
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Rounding off with zero at the end

We can round off a number say 23 or 74 to 20 and 70 by seeing the numbers lsb(right most bit) and 26 or 78 to 30 and 80.. My doubt is if this is possible in verilog codes... I want to know after converting into digital will this concept be…
Satheesh.R
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