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In the UVM test I declare and start the sequences, but the output from separate sequences with the same parameters are "related" somehow(see example at the bottom), so when I do cross coverage I only coverage 12.5% of the cases, what is causing this? How can I make the output of the two sequences independent and random?

//declare
ve_master_sequence#( 8,`num_inputs) x_agent_sequence_inst;
ve_master_sequence#( 8,`num_inputs) y_agent_sequence_inst;
//build_phase
x_agent_sequence_inst = ve_master_sequence#( 8,`num_inputs)::type_id::create("x_seq");
y_agent_sequence_inst = ve_master_sequence#( 8,`num_inputs)::type_id::create("y_seq");
//run_phase
x_agent_sequence_inst.start(multadd_env_inst.ve_x_agent_inst.sequencer);
y_agent_sequence_inst.start(multadd_env_inst.ve_y_agent_inst.sequencer);

The environment contains 4 master agents, two 32 bit, two 8 bit. The same parameterized sequence is run on all the agents

// within the sequence
virtual task body();
  `uvm_info("ve_master_sequence", $sformatf("begin body()"), UVM_MEDIUM);
    for(int i=0; i<length; i++) begin
    req = ve_seq_item#(data_width)::type_id::create("req");
    start_item(req);

  while(!req.randomize() with { 
     data <= (2**data_width)-1;
     delay  dist { [0:1] := 2, [2:6] := 1};  
     });

    finish_item(req);
    get_response(req);
    end
    #1000;
endtask

I replaced the req.randomize() with $urandom_range, which worked but it means losing all the constrained random abilities of systemverilog.

When I run the code, and do cross coverage there is a relationship between the output of the sequencers that are the same size,

when y = 0  is always x = 79 or 80
when y = 1  is always x = 80 or 81
when y = 2  is always x = 81 or 82
....
when y = 51 is always x = 130 or 131
when y = 52 is always x = 131 or 132

etc..

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  • What is the question? Please clarify. – Hida Dec 09 '15 at 16:14
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    Are there any constraints inside the ve_seq_item class? Try switching out your `while(!req.randomize()...` with ``if(reg.randomize()...) else `uvm_error(...)``. This will report any errors instead of getting stuck in the while loop. – Hida Dec 09 '15 at 16:33
  • the "if" change did not report any errors, but perhaps this is a clue, if I change the variable name of the sequence, the relationship between the numbers output by the sequence changes, thanks for the comments – StanOverflow Dec 10 '15 at 16:41
  • there are no constraints in the seq_item class – StanOverflow Dec 10 '15 at 16:41
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    Hmm.. Could be something weird in the way your tool performs randomizations. Perhaps the pseudo-randomization is not arbitrary enough and causing the relationship. Sounds strange, but changing the variable name may somehow change the conditions for the randomization and thus change the relationship. What tool are you using? What UVM version are you running? Make sure that the use_uvm_seeding(part of uvm_object) variable is set to 1. – Hida Dec 11 '15 at 12:36

2 Answers2

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Apparently UVM uses its parent Random Number Generator and the sequence name to create a new RNG for the sequence. This is to give good random stability.

Try changing the names for the sequences to make them more unique. I am assuming that longer unique strings give a higher degree of randomization.

Hida
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Inside the sequence class was this loop creating sequence items. The explanation is (as already said above) UVM uses the class hierarchy for to create the random seed, which gives good random stability

for(int i=0; i<1000; i++) begin
     //this caused the error
     req = ve_seq_item#(data_width)::type_id::create("req");

     //this fixed it
     req = ve_seq_item#(data_width)::type_id::create($sformatf("req_%1d", i));
     //randomizing the sequence item with the loop variable
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