Hi i was just curious what would be the gate cost of combinational 16 bit Ripple carry adder, and 16 bit (Two Level) Carry Look Ahead Adder. Thanks
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FPGA or ASIC target? – alex.forencich Nov 24 '15 at 00:16
1 Answers
Quoting from wikipedia:
The layout of a ripple-carry adder is simple, which allows for fast design time; however, the ripple-carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder. The gate delay can easily be calculated by inspection of the full adder circuit. Each full adder requires three levels of logic. In a 32-bit ripple-carry adder, there are 32 full adders, so the critical path (worst case) delay is 3 (from input to carry in first adder) + 31 * 2 (for carry propagation in later adders) = 65 gate delays.
1 bit Ripple carry adder had 1 full adder. Therefore, 16 bit Ripple carry adder has 16 full adders.
You may want to refer to this diagram on how many are there in a full adder circuit.
The rest will serve as your homework.

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