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My problem is that I have to pass a generic from a SystemVerilog module to a VHDL entity of type std_logic, that will be directly used inside that entity in signal assignments.

entity foo is
    generic( my_generic : std_logic);
    port (...);
end foo;

architecture arc of foo is
...
begin
    my_signal <= not(my_generic);
    ...
end arc;

However, my_signal is always 'U', whatever type (integer, std_logic, bit, reg, wire) is the parameter in SV. The tool I'm using is Modelsim 10.3b. There are some workarounds, like declare it as an integer in VHDL and then cast it to a std_logic_vector of width 1, but I like to know if there is a smarter way. Am I missing something? Is it allowed to pass std_logic as a parameter? Can this also cause problems during synthesis with Xilinx ISE?

Thanks in advance.

JHBonarius
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arandomuser
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    What happens if you use a boolean to boolean mapping, instead: `generic(my_generic: boolean);` and `my_signal <= '0' when my_generic else '1';`? – Renaud Pacalet Nov 05 '15 at 11:23
  • @RenaudPacalet thank you for the fast reply, the problem is that I have a lot of comparisons `if(my_signal = MY_GENERIC)then`, where my_signal has to be a std_logic, so make the generic a boolean is of no help... – arandomuser Nov 05 '15 at 15:23
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    I understand your point but I just suggested to first identify whether the problem comes from your VHDL code or from the Modelsim SystemVerilog to VHDL mapping. The simple experiment I suggest should help, I think. – Renaud Pacalet Nov 05 '15 at 16:39

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