While using SystemVerilog, this must be one of the very first thing to learn. This is very common and important method in SystemVerilog. Either use $size
or arrayname.size
method.
Following is your sample code, I have used arrayname.size
method, the same can be accomplished by $size(arrayname)
.
for(int i = 0 ; i < data.size ; i+=2 )
begin // no curly braces here, except constraints
foo(data[i],data[i+1]);
end
There is also a foreach
loop for which the size of array need not to be known. The above mentioned task can be called as follows. Here you want i+1th element to exist, so you must use size method. Henceforth there is no extra benefits of this method.
foreach(data[i])
begin
if(i%2 == 0 && i+1<data.size)
foo(data[i],data[i+1]);
end
Note that i
is an internal variable here, no need to declare i
.
More information can be available at this link. SystemVerilog LRM 1800-2012 must be very helpful.