Initialization priority in verilog

Question

Hello verilog experts,

In the verilog code below, can I be 100% that top.test.p will be systematically initialized to 200?

Or will I have a race between the variable initialization and the initial statement? In other words, some simulators will give me top.test.p == 100 and others top.test.p == 200?

Thanks

    module test;
       parameter real P = 1e3;
       real P=p;
    endmodule    

    module top;
      test #(100) test();
      initial
       begin
       // override the variable initialization (race condition????)
       test.p = 200;
      end
    endmodule

Do you mean _parameter_ by `parameter real P = 1e3`? I guess it must be `p` instead of `P` (can be typo mistake), also it must be variable, not a parameter. Parameters can not be changed in procedural block, they can only be over-ridden while instantiating or by `defparam`. — sharvil111, Nov 04 '15 at 06:35

score 3 · Answer 1 · answered Nov 02 '15 at 23:56

A SystemVerilog compliant simulator must execute variable declaration initialization before any initial or always process begins. So top.test.p should be 200

Section 6.8 says

Setting the initial value of a static variable as part of the variable declaration (including static class members) shall occur before any initial or always procedures are started (also see 6.21 and 10.5 on variable initialization with static and automatic lifetimes).

This ordering was undefined in Verilog.

Initialization priority in verilog

1 Answers1