Can we can have print statement in classes without any function/task in system verilog

Question

Can we can have print statement in classes without any function/task in SystemVerilog?

http://www.edaplayground.com/x/8Y8

class A;
 int x=10;
 $display("x=%d",x);
 endclass

module abc;
 A a;
 initial begin
   a=new();
 end
endmodule

It would help to explain why you think you want to do this. Is it to help debug your code? There are ways of setting breakpoints and executing print statements. But in any case, you need to latch on to a particular procedural statement to specify _when_ you want the print statement to occur. — dave_59, Nov 12 '15 at 17:03

toolic · Accepted Answer · 2020-04-07T20:40:59.930

No. According to the IEEE Std 1800-2012, section 8.3 "Syntax", a class may only contain the following items:

class_item ::= 
{ attribute_instance } class_property
| { attribute_instance } class_method
| { attribute_instance } class_constraint
| { attribute_instance } class_declaration
| { attribute_instance } covergroup_declaration
| local_parameter_declaration ;
| parameter_declaration7 ;
| ;

A $display statement may only occur in a procedural block (initial, always, final) or a task/function body.

Typically, you need to create a display function in the class, then call it explicitly.

score 0 · Answer 2 · answered Nov 12 '15 at 15:19

This is not possible. Either you have to print in a dedicated task/function or in the class constructor.

LRM states that: A display/monitor/strobe/write statement may only occur in a procedural block or in a task/function body.

We can display the default values of variables, when object is created as follows. A better option is using display in constructor itself.

class A; 
int x=10; 
function void new(); // constructor
  $display("x=%d",x); 
endfunction
endclass

"void" not allowed for constructosr. – Mihai Hangiu Nov 26 '20 at 04:58 — Mihai Hangiu, Nov 26 '20 at 04:58

Can we can have print statement in classes without any function/task in system verilog

2 Answers2