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I am trying to force some internal nodes in my design. One thing I am trying to force is a member of a struct.

When I try to do this:

module struct_force;

   struct {
      logic a;
      logic b;
      logic c;} d;

   initial begin
      force d.a  = 1;
      $display(d);
   end
endmodule

Incisive gives me an error:

Illegal use of a bit-select, part-select, member-select or mda element [9.3.1(IEEE)]

But VCS appears to be happy with it: See EDA playground example

From IEEE-1800 I see this related to force:

The left-hand side of the assignment can be a reference to a singular variable, a net, a constant bit-select of a vector net, a constant part-select of a vector net, or a concatenation of these.

I am having trouble parsing that sentence to figure out who is wrong: Is Incisive preventing me from doing something I should be able to do, or is VCS playing fast and loose with the spec?

If this is in fact illegal, what is work around to force just part of a struct?

nguthrie
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1 Answers1

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The key term in the above sentence is singular variable. The variable you are trying to force is an unpacked struct, which is not a singular variable; it is an aggregate variable.

And if you turn it into a packed struct, you run into the sentence that follows the one you quoted: "It shall not be a bit-select or a part-select of a variable..."

Nets are effectively broken down into individual scalar bits whose value is a resolution function of the drivers of that net. A force becomes just another driver of that net.

It's not impossible to add this as an enhancement to the LRM, but a tool would have to break the variable up into individual bits - every regular assignment to that variable would have to be done bit-by bit to check if one of the bits was in a forced state.

dave_59
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