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Questions tagged [modelsim]

ModelSim is a popular simulator and debugging environment for VHDL, Verilog and SystemC. It is used in electronic design automation for development and verification of electronic (mainly digital) modules and systems for implementation on field-programmable gate arrays or integrated circuits.

ModelSim is a product by Mentor Graphics to simulate systems written in one of the hardware description languages (HDLs) VHDL or Verilog or the system-level modeling language SystemC.

Depending on the license, ModelSim offers all or a subset of the following features:

  • Source code editor
  • Compiler
  • Simulator
  • Waveform viewer
  • Interactive debugging such as breakpoints, stepping etc.
  • Signal tracing (dataflow) analysis
  • Code coverage analysis
  • Functional coverage analysis
  • Project file management

ModelSim integrates these features in a single configurable GUI, however, it can also be scripted via the Tcl language and controlled through command-line parameters which allows for automation of simulation and verification tasks.

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modelsim error vsim-3421 when run from xilinx ISE 14.2

I designed and tested my VHDL code. I used ISIM (xilinx simulator) to test the code. ISIM was buggy so i switched to modelsim SE 10c. when i run modelsim through xilinx ise i get following error in modelsim Fatal: (vsim-3421) Value -14 is out of…
user3056350
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VHDL output is undifined in simulation but compilation is passed fine

I am a fresh student and the assignment is to build 3 components with testbench and then to arrange them into one structure. All 3 components I have built work great but when I put them together one of the the outputs stays undefined. I tried to…
user2651144
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detect a change on a std_logic_vector

i had a question about detecting a change on a std_logic_vector(4 downto 0). Here is my code : LIBRARY IEEE; library work; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; Entity CHANGE_CUR_GRP is port( MCLK : in std_logic; RST_N …
mugen54
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I'm trying to implement a convolution encoder. I have attached my code. I am a beginner in verilog and I don't think my testbench is working properly

`timescale 1 ns/1 ns module VIT_ENC (Vx,Ux,tb_en,clock,reset); `include "params_b213.v" output [`n-1:0] Vx; input [`k-1:0] Ux; input tb_en; input clock; input reset; reg [`m:0] encoder_reg; always @(posedge clock…
Vijethri Avadhany M S
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Why do I get this syntax error in ModelSim (Verilog)?

I get this error "** Error: (vlog-13069) C:/Users/pc/Documents/ModelSim Proj/ram_system.v(60): near "(": syntax error, unexpected '(', expecting '''." in Modelsim using Verilog, I do not know where that error is because there is no "(" in the line,…
Queries17
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vhdl error: near "IN": (vcom-1576) expecting STRING or IDENTIFIER or << or '('

This is for a university project. I'm programming a Mealy Box and I have reached an error I had never found, and I can't find solution online; there are similar, but still don't work. The error is: near "IN": (vcom-1576) expecting STRING or…
João Lima
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Priority case with for loop inside always_comb Procedural block gives error?

I am trying to build a static priority encoder, for example, 0011101010------>0010000000 Basically the index with highest value should be one and other indices must be zero. I have tried the following code with modelsim and it gives error saying: **…
PrashantYadav
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Systemverilog Generate mailboxes

How can i generate many mailboxes, for example with generate endgenerate and the how to i put data to one for them. I tried doing generate for (genvar i=0; i<10; i++) begin mailbox test = new(); end endgenerate and it creates 10…
el pass
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verilog flop RTL simulation

Assume we have a D-flip-flop. in RTL simulation (No t_hold and t_setup here), If its data input and clk changes at the same time, what the output should be ? The value before clk rise or the value after it ? To make it even harder, If a data_in and…
Ayman Mouallem
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VHDL Counter Error (vcom-1576)

guys im trying to code a simple counter in VHDL but i always get this error: Error: C:/Users/usrname/dir1/dir2/dir3/counter.vhd(22): near "rising_edge": (vcom-1576) expecting == or '+' or '-' or '&'. Here is my Code: library ieee; use…
josepchappa
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error: cannot convert 'bool' to 'svLogic*' in assignment

We are working on the system verilog DPI calls. While compiling the C++ file we are getting the errors like this: error: cannot convert 'bool' to 'svLogic*' in assignment Here svLogic is 4-state variable. The VCS simulator has predefined…
Santhosh Kumar
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Multiplying two 32 bit numbers using 32 bit carry look ahead adder

I have tried to write the code in Verilog to multiply two 32 bit binary numbers using a 32 bit carry look ahead adder but my program fails to compile. the generate if condition must be a constant expression error keeps on coming in Modelsim for the…
Ritwika Chakraborty
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How to write a 32 bit "reg" of a ".v" program in Modelsim to a ".txt" file?

I need to write a 32 bit "reg" of a ".v" program in Modelsim in to a txt-type file. The variable is changing every CLK cycle and I need to store each value of it in decimal format. The program needs to write the each value just in one line.
M.Hallajian
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Testbench in VHDL

I have designed an entity multiply and an architecture which implements this entity, but I don't know how to write a testbench for that. In other words: how can I pass values to my architecture? I'm not sure if this codes is right at all, but I…
user2071938
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What's wrong with the code I made in Modelsim VHDL Code? Using Behavioral Model

I have this VHDL coding, my Boolean Expression is F(w,x,y) = wxy + wx'y' + xy + w'x'y' and I need to convert it to a Behavioral Model. My question is if I coded the Behavioral Model correctly and I think it is wrong but I don't know where the error…
Devil Blacklist
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