VHDL output is undifined in simulation but compilation is passed fine

Question

I am a fresh student and the assignment is to build 3 components with testbench and then to arrange them into one structure. All 3 components I have built work great but when I put them together one of the the outputs stays undefined. I tried to trace the signal called dat and it is fine, but probably I am not using correct syntax to assign the dat signal to data_out . The id_led_ind is the second output and it works fine but the data_out is undefined.

Here is the code (i think the problem is in lane 21 - "data_out <= dat")

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity peak_detect is
  port(
    input      : in  std_logic_vector (7 downto 0);
    data_out   : out std_logic_vector (7 downto 0);
    reset      : in  std_logic;
    clock      : in  std_logic;
    enable     : in  std_logic;
    id_led_ind : out std_logic);
end peak_detect;

architecture dataflow of peak_detect is
  signal a_big_b : std_logic;
  signal en      : std_logic;
  signal dat     : std_logic_vector (7 downto 0);
begin
  en       <= (enable or a_big_b);
  data_out <= dat;
end dataflow;

architecture structure of peak_detect is
  signal a_big_b : std_logic;
  signal en      : std_logic;
  signal dat     : std_logic_vector (7 downto 0);

  component comp_8bit is
    port(
      A   : in  std_logic_vector (7 downto 0);
      B   : in  std_logic_vector (7 downto 0);
      res : out std_logic);
  end component;

  component dff is
    port (
      data  : in  std_logic_vector (7 downto 0);
      q     : out std_logic_vector (7 downto 0);
      clk   : in  std_logic;
      reset : in  std_logic;
      en    : in  std_logic);
  end component;

  component id_sens is
    port(
      data_in : in  std_logic_vector (7 downto 0);
      led     : out std_logic);
  end component;

begin
  reg  : dff port map (data => input, q => dat, clk => clock, reset => reset, en => enable);
  comp : comp_8bit port map (A => input, B => dat, res => a_big_b);
  sens : id_sens port map (data_in => dat, led => id_led_ind);
end structure;

Answer 1

There appears to be confusion over having two architectures (dataflow and structure) for the entity peak_detect. The two architectures are mutually exclusive, and the last one analyzed is the default in absence of other configuration specifying one of the architectures directly.

For purposes of evaluating how the components are interconnected and their port mapped connections relate to the port declarations of peak_detect, the first architecture could be commented out (dataflow).

When you disregard the architecture dataflow we find there is no driver for data_out in architecture structure.

You're missing an assignment to data_out using dat as a source in architecture structure, as found in architecture dataflow. Copy or replicate the concurrent signal assignment statement data_out <= dat; into architecture structure.

You can't simply connect data_out to q in the port map of dff because the output of dff is also used as an input to id_sense.

Answer 2

dat is driven by q of dff. That is not how you connect components. port map should be used to connect ports of different components/entities, not signals of any entity to the port of another entity.