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Questions tagged [modelsim]

ModelSim is a popular simulator and debugging environment for VHDL, Verilog and SystemC. It is used in electronic design automation for development and verification of electronic (mainly digital) modules and systems for implementation on field-programmable gate arrays or integrated circuits.

ModelSim is a product by Mentor Graphics to simulate systems written in one of the hardware description languages (HDLs) VHDL or Verilog or the system-level modeling language SystemC.

Depending on the license, ModelSim offers all or a subset of the following features:

  • Source code editor
  • Compiler
  • Simulator
  • Waveform viewer
  • Interactive debugging such as breakpoints, stepping etc.
  • Signal tracing (dataflow) analysis
  • Code coverage analysis
  • Functional coverage analysis
  • Project file management

ModelSim integrates these features in a single configurable GUI, however, it can also be scripted via the Tcl language and controlled through command-line parameters which allows for automation of simulation and verification tasks.

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Scons for FPGA?

Is there somebody who has used 'Scons' as a replacement for 'make' for quite large FPGA projects? Did it ran out-of-the-box or is there still some hacking to be done for the VHDL or Verilog language? And what about the integration with…
vermaete
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Debugging Iteration Limit error in VHDL Modelsim

I'm writing VHDL code for a d-flip-flop on Modelsim and I get an error when I try to simulate it: Error: (vsim-3601) Iteration limit reached at time 400 ps. I'm not sure what it means, but I've looked through much of my source code for errors to…
user607444
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Shifter output is always 0 when using concatenation and case

I have the following code: module shifter( input[7:0] in, input[1:0] amt, output logic[7:0] out ); always_comb case(amt) 2'h0: out = in; 2'h1: out = {{in[6:0]}, 0}; 2'h2: out = {{in[5:0]}, 0, 0}; 2'h3: out = {{in[4:0]},…
jeanluc
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Why ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0?

Why does Modelsim complain about the component instantiation i1? Time: 0 ps Iteration: 1 Instance: /vhdl2_uppgift_1_extra_vhd_tst/i1 ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 LIBRARY ieee; …
Lasse Karagiannis
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VHDL - Why does using the length attribute directly on a function produce a warning?

I have a VHDL function that returns a std_logic_vector representation of a record and I want the length of that std_logic_vector. I am able to use the length attribute directly on the function. Why does this produce a warning in ModelSim? Am I…
Scott Watson
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Using VHDL Record in SystemVerilog Testbench in Modelsim

I've done research on this, but the examples that I've found on other web pages have broken links. I'm looking for an example of how to import a custom VHDL record that is contained in a package into a SystemVerilog Testbench. I'm using modelsim,…
Russell
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Modelsim signal declaration issue

With Modelsim I would like to test a code but one signal always remains uninitialized. Here a code snipped to explain the problem with Modelsim: -- Signal Declaration signal shifter : std_logic_vector(0 to 6); signal led_out_temp :…
Norick
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How to wait for Modelsim Simulations to complete before proceeding in TCL script

I am trying to execute a regression test in Modelsim. I call a TCL script which compiles my source files and launches vsim. I launch a .do file and it runs a series of testbenches which all output result files. What I am adding is an automated…
jarickc
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VHDL integer range inclusive? Difference in FPGA vs. simulation

I'm new to FPGAs. I've been doing some simple tests and I found an issue I don't fully understand. I have a 50MHz clock source. I have a signal defined as: SIGNAL ledCounter : integer range 0 to 25000000 := 0; When the ledCounter reaches…
RobC
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Ambiguous type in infix expression VHDL

I'm getting the following error in ModelSim: Error: [..]/test1_toVectorAlignment_rtl.vhd(40): Ambiguous type in infix expression; t_RAMXx8 or ieee.std_logic_1164.STD_LOGIC_VECTOR. ARCHITECTURE rtl OF test1_toVectorAlignment IS type t_RAMXx8 is array…
deinocheirus
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(Tcl?) Script for running modelsim with testbench as parameter from shell

I want to make a script, which can be executed from shell like: ./myscript -test1 or tclsh myscript.tcl -test1 I want it to open ModelSim, compile units, load a desired testbench, run simulation. Name of the test would be a parameter. I've already…
RaZ
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How can I make Modelsim exit with a specified exit code from SystemVerilog

I am trying to build a test bench in SystemVerilog using a clocking block cb_module. I am running Modelsim from the command line: vsim -c test_bench -do "run -all" Everything works fine but I can not figure out how to get Modelsim to exit and…
AxelOmega
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get dependencies of vhdl entity in modelsim

I compiled a large VHDL design in ModelSim successfully. The design is not important here, my question is about ModelSim commands for any VHDL design. Now let's say I have an entity E1 there and I want to know all the packages and entities that are…
Sadık
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verilog modelsim fpga

Sorry for Newbish question. I am trying to learn about FPGA programming. Before I spend $1K on a FPGA board: if I just want to learn Verilog, can I run it entirely in Modelsim? (I realize there are some timing issues that only show up in actual…
anon
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Is default value required for a Verilog parameter declaration?

Parameters in Verilog code is usually declared with a default value, like: parameter UP = 1; But if the parameters is always to be overridden at module instantiation, then I have also seen declaration without default value, like: parameter…
EquipDev
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