modelsim error vsim-3421 when run from xilinx ISE 14.2

Question

I designed and tested my VHDL code. I used ISIM (xilinx simulator) to test the code. ISIM was buggy so i switched to modelsim SE 10c. when i run modelsim through xilinx ise i get following error in modelsim

Fatal: (vsim-3421) Value -14 is out of range -7 to 7.

my related VHDL code is

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

library UNISIM;

use UNISIM.VComponents.all;

signal img_int : integer range -7 to 7 ;

signal add1 : integer range -7 to 7 ;

signal add2 : integer range -7 to 7 ;

process (clk)

begin

if rising_edge(clk) then

    add1 <= to_integer( signed(e(0)) ) + to_integer( signed(e(1)) ) + 

            to_integer( signed(e(2)) ) + to_integer( signed(e(3)) );


    add2 <= to_integer( signed(e(4)) ) + to_integer( signed(e(5)) ) +

            to_integer( signed(e(6)) ) + to_integer( signed(e(7)) );

end if;

end process;

img_int <= add1 + add2;

the problem line is

img_int <= add1 + add2;

Can any tell why modelsim is giving this error?

score 0 · Answer 1 · answered Oct 23 '14 at 12:36

Because the minimum possible value of 'add1' is -7. The same for 'add2'. Adding 'add1' with 'add2' gives you a minimum value of -14. That value (-14) can not be held in your 'img_int' signal.

You can extend the range of 'img_int' to e.g. integer range -14 to 14 or truncate the result.

Anyway: Try to use the 'signed' and 'unsigned' types of the liberary 'ieee.numeric_std' i.s.o. the type 'integer'.

modelsim error vsim-3421 when run from xilinx ISE 14.2

1 Answers1