I'm trying to implement a convolution encoder. I have attached my code. I am a beginner in verilog and I don't think my testbench is working properly

Question

`timescale 1 ns/1 ns

module VIT_ENC (Vx,Ux,tb_en,clock,reset);

`include "params_b213.v"

output [`n-1:0] Vx;
input  [`k-1:0] Ux;
input           tb_en;
input           clock;
input           reset;

reg [`m:0] encoder_reg;

always @(posedge clock or posedge reset)
   begin   
      if(reset)
         encoder_reg = 4'b0;
  
      if (tb_en==1'b0)
         encoder_reg = {Ux, encoder_reg[3:1]};
   end

assign Vx[1] = encoder_reg[3]^encoder_reg[1]^encoder_reg[0];
assign Vx[0] = encoder_reg[3]^encoder_reg[2]^encoder_reg[1]^encoder_reg[0];

endmodule

The always block does not work for some reason. The encoder_reg is not getting any values. How to assign values to a reg in an always block? EDIT: I am adding the test bench code also here. So we are giving some input to Ux, which has to get shifted and stored in encoder_reg. Modulo 2 addition(XOR) is performed between the bits of encoder_reg and stored in the output.

`timescale 1 ns/1 ns

module tb_VIT_ENC();

`include "params_b213.v"

wire [`n-1:0] Vx;
reg [`k-1:0] Ux;
reg tb_en;
reg clock;
reg reset;

VIT_ENC 
dut(.Vx(Vx),.Ux(Ux),.tb_en(tb_en),.clock(clock),.reset(reset));

initial
begin
    Ux=1;tb_en=0;clock=1;reset=0;
    #100;
    Ux=0;tb_en=0;clock=1;reset=0;
    #100;
    Ux=1;tb_en=0;clock=1;reset=0;
    #100;
    Ux=0;tb_en=0;clock=1;reset=0;
end

endmodule

Pavan Kumar · Answer 1 · 2022-09-01T11:48:01.857

I can see that there is no clock signal generation in the test bench. Without a positive edge on the clock signal the registers are'nt going to work. You could use the following initial block in your test bench, instead of driving clock = 1 every 100ns as written in your test bench.

initial
begin
  clock = 1'b1;
  forever #5 clock = ~clock; //Clock Generator
end

The initial block sets clock to 1 initially. The next line toggles the clock after 5ns and sets clock to 0. The forever keyword ensures the clock toggles every 5 time units forever till the end of the simulation, thus generating a square wave of period 10 time units. (Given the timescale in your code 10 time units = 10 ns)

I'm trying to implement a convolution encoder. I have attached my code. I am a beginner in verilog and I don't think my testbench is working properly

1 Answers1