VHDL Counter Error (vcom-1576)

Question

guys im trying to code a simple counter in VHDL but i always get this error:

Error: C:/Users/usrname/dir1/dir2/dir3/counter.vhd(22): near "rising_edge": (vcom-1576) expecting == or '+' or '-' or '&'.

Here is my Code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter is
port (
EXT_RST : in std_logic;
EXT_CLK : in std_logic;
EXT_LED : out std_logic_vector(7 downto 0)
);
end counter;

architecture fast of counter is

signal count : std_logic_vector(7 downto 0);

begin
process(EXT_CLK, count)
  begin
    if (EXT_RST = '1') then
    count <= "00000000";
    elseif rising_edge(EXT_CLK) then
    count <= count + '1';
    end if;
 end process;
EXT_LED <= count;
end fast;

Has anyone an idea why im getting this error?

Hint: `elseif` is not a VHDL keyword. – wjl Oct 13 '15 at 13:01 — wjl, Oct 13 '15 at 13:01
when i use `else if` i get even more errors :S – josepchappa Oct 13 '15 at 13:04 — josepchappa, Oct 13 '15 at 13:04

score 3 · Accepted Answer · 2015-11-03T16:45:12.793

Besides the elsif Lars Asplund suggested using in his comment use type conversions for `count:

count <= std_logic_vector(unsigned(count) + 1);

or use package numeric_std_unsigned (VHDL -2008 only) instead of numeric_std.

Notice the 1 instead of '1' and type conversions. Those aren't needed with numeric_std_unsigned which has a "+" adding operator function with this signature:

[STD_ULOGIC_VECTOR,STD_ULOGIC return STD_ULOGIC_VECTOR]

Using package numeric_std you can also make count an unsigned instead of std_logic_vector and convert for the LED assignment -

EXT_LED <= std_logic_vector(count);

Also, count doesn't need to be in the process sensitivity list:

process(EXT_CLK)

There are no assignments in the process where the value of count is used except on the clock edge.

Modifying your code with the first suggestion and indenting (which helps show the sensitivity list doesn't need count:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter is
    port (
        EXT_RST : in std_logic;
        EXT_CLK : in std_logic;
        EXT_LED : out std_logic_vector(7 downto 0)
    );
end counter;

architecture fast of counter is

signal count : std_logic_vector(7 downto 0);

begin
process(EXT_CLK)
  begin
    if (EXT_RST = '1') then
        count <= "00000000";
    elsif rising_edge(EXT_CLK) then
        count <= std_logic_vector(unsigned(count) + 1);
    end if;
 end process;
    EXT_LED <= count;
end fast;

This analyzes, elaborates and will simulate.

This prompts the question of how EXT_RST and EXT_CLK are derived should you actually synthesize your design. If they are from buttons (particularly the clock), debounce could be necessary even with membrane switches which can age and later bounce.

VHDL Counter Error (vcom-1576)

1 Answers1

Linked