Why do I get this syntax error in ModelSim (Verilog)?

Question

I get this error "** Error: (vlog-13069) C:/Users/pc/Documents/ModelSim Proj/ram_system.v(60): near "(": syntax error, unexpected '(', expecting '''." in Modelsim using Verilog, I do not know where that error is because there is no "(" in the line, Can you help me to find the error and fix it?

Here is the complete code:

module RAM6116_system ();
reg[1:0] state; 
reg[1:0] next_state; 
reg inc_adrs; 
reg inc_data; 
reg ld_data; 
reg en_data; 
reg Cs_b; 
reg clk; 
reg Oe_b; 
reg done; 
reg We_b; 
reg[7:0] Data; 
reg[7:0] Address; 
wire[7:0] IO;



initial begin
inc_adrs = 1'b0; 
inc_data = 1'b0; 
ld_data = 1'b0; 
en_data = 1'b0; 
clk = 1'b0;
Cs_b = 1'b0; 
Oe_b = 1'b0; 
done = 1'b0; 
We_b = 1'b1; 
end

RAM6116 RAM1 (Cs_b, We_b, Oe_b, Address, IO);

always @(state or Address) 
begin : control
ld_data = 1'b0; 
inc_data = 1'b0; 
inc_adrs = 1'b0; 
en_data = 1'b0; 
done = 1'b0;
We_b = 1'b1; 
Cs_b = 1'b0; 
Oe_b = 1'b1;

case(state)

0:  begin
        Oe_b = 1'b0; 
        ld_data = 1'b1; 
        next_state = 1;
    end
1:  begin
        inc_data = 1'b1; 
        next_state = 2;
    end
2:  begin
        We_b = 1'b0; 
        en_data = 1'b1; 
        inc_adrs = 1'b1; 
        next_state = 3;
    end
3:  begin //this is line 60, where the error is, but I don't know how to fix it
        if (Address == 8'b00100000)
    begin
        done = 1'b1; 
        next_state = 3;
    end 
    else 
        begin
            next_state = 0;
        end
    end
endcase
end

always @(posedge clk) 
begin : register_update
    state <= next_state; 
    if (inc_data == 1'b1) 
    begin
        Data <= Data + 1;
    end 
    if (ld_data == 1'b1) 
    begin
        Data <= unsigned(IO);
    end
    if (inc_adrs == 1'b1)
    begin
        Address <= #1 Address + 1;
    end
end

always #100 clk = ~clk; 
assign IO = (en_data ==1'b1) ? Data : 8'bZZZZZZZZ;
endmodule

score 0 · Answer 1 · answered Jul 23 '22 at 19:59

There certainly is a ( in the line with the error message. The problem is unsigned is reserved keyword and you problems meant to use $unsigned(IO) instead. Had you written

Data <= unsigned'(IO);

That would have been legal syntax for a cast to unsigned in SystemVerilog; but without the ', it is illegal syntax.

Note that since Data and IO are both 8-bits wide, there is no need for any of these. You could have just written:

Data <= IO;

Why do I get this syntax error in ModelSim (Verilog)?

1 Answers1