Questions tagged [modelsim]

ModelSim is a popular simulator and debugging environment for VHDL, Verilog and SystemC. It is used in electronic design automation for development and verification of electronic (mainly digital) modules and systems for implementation on field-programmable gate arrays or integrated circuits.

ModelSim is a product by Mentor Graphics to simulate systems written in one of the hardware description languages (HDLs) VHDL or Verilog or the system-level modeling language SystemC.

Depending on the license, ModelSim offers all or a subset of the following features:

Source code editor
Compiler
Simulator
Waveform viewer
Interactive debugging such as breakpoints, stepping etc.
Signal tracing (dataflow) analysis
Code coverage analysis
Functional coverage analysis
Project file management

ModelSim integrates these features in a single configurable GUI, however, it can also be scripted via the Tcl language and controlled through command-line parameters which allows for automation of simulation and verification tasks.

756 questions

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1 answer

Finding when a certain signal has a particular value in Modelsim using tcl

I'm trying to speed up debugging. In a large trace I'm search for particular values of a signal. Im using QuestaSim 10.0b under linux. I already found out that can be done in Modelsim/QuestaSim with the following command searchlog -expr { stream ==…

tcl modelsim questasim

asked Nov 24 '14 at 04:39

sebs

4,566
3
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28

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3 answers

How can I read binary data in VHDL/modelsim whithout using special binary formats

I am writing a VHDL test bench for a ethernet MAC. The testbench consists of a package and an combined entity + architecture file. I want to read the ethernet frames that the testbench will send to the MAC from a binary file which I exported from…

io vhdl modelsim

asked Jan 05 '13 at 16:14

youR.Fate

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2 answers

ModelSim Message Viewer Empty

I'm currently using Modelsim 10.1 alongside ISE 13.4 and run a very simple test bench. All code is VHDL. I ran into trouble using VHDL's assert statement the other day: Errors and warnings are output to the transcript. However, there are no messages…

message vhdl viewer modelsim

asked Mar 14 '12 at 19:55

FRob

3,883
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40

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3 answers

Modelsim and GHDL cannot dump vhdl user-defined signal types into vcd?

I'm trying to dump internal signals from a simulation executed either by modelsim or ghdl. Everything works fine using: For modelsim, add vhdl sources, and compile all then: vsim -novopt work.uut_testbench vcd file ../uut.vcd; vcd limit…

signals vhdl modelsim ghdl

asked Mar 11 '12 at 13:02

Tarek Eldeeb

votes

1 answer

Modelsim VHDL Array Initialization gives warning (vcom-1320)

I'm using Modelsim's VHDL-Compiler (vcom) for code linting with SublimeText (VHDL 2008). While initializing an array of standard_logic_vector I get the following warning: vcom: warning Warning - (vcom-1320) Type of expression "(OTHERS => '0')" is…

arrays initialization vhdl fpga modelsim

asked Jul 14 '20 at 12:26

Peter

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3 answers

How to restart a Verilog simulation in Modelsim

I'm trying to debug a Verilog module. I find it tedious to have to stop a simulation, modify code, and then go through the process of starting the simulation again. Is there an easier way?

debugging module verilog modelsim

asked Mar 10 '11 at 20:56

node ninja

31,796
59
166
254

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0 answers

The globally static error (modelsim vs quartus)

This simple test leads to an error while compiling with modelsim whereas Quartus is fine to go through the whole synthesis/fitter process. library ieee; use ieee.std_logic_1164.all; entity submodule is port( four_bits_input : in …

vhdl modelsim quartus

asked May 17 '18 at 13:02

grorel

1,408
15
21

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1 answer

Cocotb VHDL need for FLI

I am currently setting up a Cocotb based verification environment. I just discovered that the example provided with Cocotb don't work in my case if using VHDL, because my simulator has no FLI (foreign language interface). I get the following…

vhdl verilog modelsim intel-fpga cocotb

asked Nov 09 '16 at 16:31

user1654361

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4 answers

Testing VHDL / FPGA Using Python and A Simulator

The standard way to test VHDL code logic is to write a test bench in VHDL and utilize a simulator like ModelSim; which, I have done numerous times. I have heard that instead of writing test benches in VHDL, engineers are now using Python to test…

python testing vhdl fpga modelsim

asked Mar 02 '16 at 01:24

DigitalOne

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2 answers

Procedure call in loop with non-static signal name

In some testbench code I use a procedure to do something with a signal. I then use this procedure multiple times in sequence on different signals. This works fine as long as I explicitly define the signal; as soon as I index signals in a loop it…

vhdl modelsim

asked Jun 25 '15 at 08:25

mbschenkel

1,865
1
18
40

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1 answer

How to concatenate strings with integer in report statement?

I'm having trouble getting the following report statement to work: report "ERROR: instruction address '" & CONV_INTEGER(a(7 downto 2)) & "' out of memory range." severity failure; Where a is of type in std_logic_vector(31 downto 0). The error I'm…

vhdl modelsim intel-fpga quartus

asked Apr 16 '15 at 18:20

Nate

26,164
34
130
214

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2 answers

ModelSim error: Instantiation of 'OR' failed

I am having trouble with running a Verilog project with ModelSim Student Edition 10.2c. Everything compiles without error, however I get the following error at runtime: # vsim -gui work.testbench # Loading work.testbench # Loading…

verilog instantiation modelsim

asked Nov 24 '13 at 23:35

CodeKingPlusPlus

15,383
51
135
216

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2 answers

modelsim: find processes/variables

I would like to write a nice function that adds signals and process variables to the wave. While it's quite easy with signals, I don't know how to do it with variables. I would expect something like "find processes" and "find variables" in analogy…

vhdl modelsim

asked Nov 18 '13 at 14:25

Andy

votes

1 answer

Weak 'H', Pullup on inout bidirectional signal in simulation

Is there a way to tell the simulator (I'm using Modelsim) to pull a signal to weak 'H' when it's not being driven by either bidirectional interface? For example if I have an I2C signal I2C_SDA that is declared as an inout from 2 modules. One is…

vhdl modelsim

asked Oct 01 '13 at 13:32

Russell

3,384
4
31
45

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3 answers

Power function in vhdl

I want to make power function using vhdl where the power is floating number and the number is integer (will be always "2"). 2^ some floating number. I use ieee library and (fixed_float_types.all, fixed_pkg.all, and float_pkg.all). I thought of…

vhdl modelsim

asked Apr 28 '13 at 19:09

user1673892

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