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I have this VHDL coding, my Boolean Expression is F(w,x,y) = wxy + wx'y' + xy + w'x'y' and I need to convert it to a Behavioral Model. My question is if I coded the Behavioral Model correctly and I think it is wrong but I don't know where the error is in my code?

Code:

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
entity My_Act41 is 
    Port ( W : in STD_LOGIC; 
           X : in STD_LOGIC; 
           Y : in STD_LOGIC; 
           F : out STD_LOGIC); 
end My_Act41; 
architecture Behavioral of My_Act41 is 

process(W,X,Y)
begin 

if((W and X and Y) = "1" and (W and not X and not Y) = "1" and (X and Y) = "1" and (not W and not X and not Y) = "1") then
    F<= '1';
else
    F<= '0';
end if
end process

end Behavioral;
Devil Blacklist
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  • What makes you think is wrong? Which are the simulation results? What is your testbench? – Fra93 Nov 09 '22 at 08:19
  • However there is no `==` operator in VHDL https://redirect.cs.umbc.edu/portal/help/VHDL/operator.html – Fra93 Nov 09 '22 at 08:20
  • Your code contains syntax errors. `if..else` statements can only be used in procedural code regions, eg. a process. You have also use equality function `=` when you should be using assignment `<=` . Finally, `if` statement requires `then` and `end if`. I suggest running your code through a compiler to discover such trivial errors. – Tricky Nov 09 '22 at 08:20
  • it's my first time using VHDL Behavioral Model Coding, there's no simulation result the compilation error. and it wasn't just VHDL I need to use Behavioral Model – Devil Blacklist Nov 09 '22 at 09:38
  • I reviewed what I gradually understood and fixed it but it's still wrong, how is the correct coding of the Behavioral Model and DataFlow Model?? – Devil Blacklist Nov 09 '22 at 11:01
  • I dont really understand how boolean expression can be "behavioural" or "data flow". Often these questions are part of university courses and have little use in real life. Simply write the expressions how you need them. – Tricky Nov 09 '22 at 16:50

1 Answers1

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The use of Behavioral Model in simple explanation is by word of Logic gates rather in DataFlow Model if you know it is by symbol.

Note: Correct me if I'm wrong that's how I understand VHDL using Behavioral Model and Dataflow Model coding

Behavioral Model Code:

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
entity My_Ac41 is 
    Port ( W : in STD_LOGIC; 
           X : in STD_LOGIC; 
           Y : in STD_LOGIC; 
           F : out STD_LOGIC); 
end My_Ac41; 
architecture Behavioral of My_Ac41 is 
begin 
F <= (W and X and Y) or (W and not X and not Y) or (X and Y) or (not W and not X and not Y); 
end Behavioral;
LZS Tanjiro
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  • Im now sure how this is an answer to the question above, which doesnt really have a question in it. – Tricky Nov 09 '22 at 16:51