Multiplying two 32 bit numbers using 32 bit carry look ahead adder

Question

I have tried to write the code in Verilog to multiply two 32 bit binary numbers using a 32 bit carry look ahead adder but my program fails to compile. the generate if condition must be a constant expression error keeps on coming in Modelsim for the part 'if(store[0]==1)' and 'if(C[32]==1)'

This is the algorithm that I followed:

Begin Program
Multiplier = 32 bits
Multiplicand = 32 bits
Register = 64 bits
Put the multiplier in the least significant half and clear
the most significant half
For i = 1 to 32
Begin Loop
If the least significant bit of the 64-bit register
contains binary ‘1’
Begin If
Add the Multiplicand to the Most Significant
Half using the CLAA
Begin Adder
C[0 ] = ’0’
For j = 0 to 31
Begin Loop
Calculate Propagate P[j] = Multiplicand[j]^ Most Significant Half[j]
Calculate Generate G[j] =
Multiplicand[j]·Most Significant Half[j]
Calculate Carries C[i + 1] = G[i] + P[i] ·
C[i]
Calculate Sum S[i] = P[i] Å C[i]
End Loop
End Adder
Shift the 64-bit Register one bit to the right 
throwing away the least significant bit
Else
Only Shift the 64-bit Register one bit to the
right throwing away the least significant bit
End If
End Loop
Register = Sum of Partial Products
End Program

Code:

module Multiplier_32(multiplier,multiplicand,store);
  output store;
  input [31:0]multiplier,multiplicand;
  wire [63:0]store;
  genvar i,j;
  wire g=32;
  wire [31:0]P,G,sum;
  wire [32:0]C;
  assign store[31:0]=multiplier;

  generate for(i=0;i<32;i=i+1)
  begin
    if(store[0]==1)
    begin
      assign C[0]=0;
      for(j=0;j<32;j=j+1)
      begin
        assign P[j]= multiplicand[j]^store[g];
        assign  G[j]=multiplicand[j]&store[g];
        assign  C[j+1]=G[i]|(P[i]&C[j]);
        assign  sum[j]=P[i]^C[j];
        assign g=g-1;
      end

      assign store[63:32]=sum[31:0];

      if(C[32]==1)
      begin
        assign store[62:0]=store[63:1];
        assign store[63]=1;
      end
      else 
      begin
        assign store[62:0]=store[63:1];
        assign store[63]=0;
      end
    end
    else
    begin
      assign store[62:0]=store[63:1];
      assign store[63]=0;    
    end
  end
endgenerate 
endmodule

I have added endgenerate. the error that is showing is ' the generate if condition must be a constant expression' — Ritwika Chakraborty, Apr 26 '15 at 06:14
You're using `generate` construct in a wrong way. It is should be used for loops to mimic multiple instants, but you're trying to use it as C-like `for-loop`. — Qiu, Apr 26 '15 at 06:30

score 0 · Answer 1 · answered Apr 27 '15 at 17:30

A generate block is evaluated at compile/elaboration time. They are used to construct hardware from patterns and not to evaluate logic. The value of store[0], C[32], and all other signals are unknown at this time. The only know values are parameters and genvars.

In this case, a combinational block (always @*) will fulfill your functionality requirements. Replace all your wire with reg, but all your assignments inside a always @*, and remove all the assign keywords (assign should not be used inside an always block).

module Multiplier_32(
    input [31:0] multiplier, multiplicand,
    output reg [63:0] store
  );

integer i,j;
integer g;
reg [31:0] P,G,sum;
reg [32:0] C;

always @* begin
  g = 32;
  store[31:0]=multiplier;
  for(i=0;i<32;i=i+1) begin
    // your code here, do not use 'assign'
  end
end
endmodule

Multiplying two 32 bit numbers using 32 bit carry look ahead adder

1 Answers1