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Questions tagged [modelsim]

ModelSim is a popular simulator and debugging environment for VHDL, Verilog and SystemC. It is used in electronic design automation for development and verification of electronic (mainly digital) modules and systems for implementation on field-programmable gate arrays or integrated circuits.

ModelSim is a product by Mentor Graphics to simulate systems written in one of the hardware description languages (HDLs) VHDL or Verilog or the system-level modeling language SystemC.

Depending on the license, ModelSim offers all or a subset of the following features:

  • Source code editor
  • Compiler
  • Simulator
  • Waveform viewer
  • Interactive debugging such as breakpoints, stepping etc.
  • Signal tracing (dataflow) analysis
  • Code coverage analysis
  • Functional coverage analysis
  • Project file management

ModelSim integrates these features in a single configurable GUI, however, it can also be scripted via the Tcl language and controlled through command-line parameters which allows for automation of simulation and verification tasks.

756 questions
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VHDL wrong RAM beahviour on reading

After 1 day of working on the same issue, maybe it is time to ask on stackoverflow :( In my project I have an entity RAM which has the following code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use…
pittuzzo
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generate signal assignmen in vhdl

I have a question. I want to use generate to signal assignment. but simulator takes me an error. the error is : " Illegal target for signal assignment." and "Unknown identifier A0_i." architecure sss of fff is signal A0_0 : bit ; signal A0_1 : bit…
ali.329
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TCL wildcard/glob usage within file name

I have code that is like this: ... proc myProc {first last} { for { set i $first } { $i <= $last } { incr i } { set i_cur "PlainText$i" [glob ./../myDir/${i_cur}*] } } When I run this, any file that has nothing…
Raj
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An ALU in Verilog, lack of output while simulating

I write an simple ALU in verilog like this: input [15:0] in; output reg [15:0] out; reg [15:0] r [0:7]; reg [3:0] opcode; reg [3:0] outreg; reg [3:0] var1, var2; reg [15:0] a1, a2; parameter STO = 4'b0000; parameter ADD = 4'b0001; parameter MUL =…
Zh.Z
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Verilog code 2 errors i can't find: Would be grateful for an extra pair of eyes to spot a mistake i might've overlooked

I'm writing a verilog code where i'm reading two files and saving those numbers into registers. I'm then multiplying them and adding them. Pretty much a Multiplication Accumulator. However i'm having a hard frustrating time with the code that i…
user3859049
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while loop inside a for loop

hi guys i wrote a while loop inside a for loop but it is not working is there something wrong with my coding? always@ (posedge clk) begin if (delay) D = 1; else D = 0; if (a) begin for (g=0;g<10;g=g+1) begin high <=…
Avelyn Goh
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ModelSim 10.1c fatal error

I'm facing a big problem with ModelSim 10.1c. I'm trying to simulate an UVM code but the following error has arising: UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(215) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2 # UVM_INFO…
saketa
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T FlipFlop Verilog

I cannot get a T-Flipflop from a D flipflop to work in Modelsim even after it came directly from class notes. It must be something simple I'm just overlooking. module D_FF (q, Clk, reset_n,d); output q; input Clk, reset_n, d; reg …
Mark
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I get this error vlog-13069

First of all, sorry for my English skills. I am studying Verilog and I have this code module paralelo_serie ( data_in,clk, D_serie, nSyn, Done ); input wire [12:0] data_in; input clk; output reg D_serie, nSyn, Done; genvar i; 84 if (data_in == 0)…
Pedro
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System task or function '$value$plusarg' is not defined -> Warning : Verilog

I am trying to learn how to use $value$plusarg. I have picked up the following code from somewhere. module test; integer i, r; initial begin r = $value$plusarg("myint=%d", i); $display("Value is %0d", i); end endmodule When I tried to run it,…
ssgr
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Parameterized function errors

I am trying to write the following systemverilog code where different parameters can be used for functions, so the same functions can be reused just by changing parameters instead of using parameterized modules. My following code compiles without…
Shahriar
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Modelsim/Questasim: Unknown entity . Use expanded name

I'm using QuestaSim, which is supposedly the same thing as ModelSim but 64-bit. I'm trying to run a test bench for an assignment due in class tomorrow. The assignment is done and all I need is the test bench, but QuestaSim is being annoying as…
PowerOfKaishin
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ModelSim Register is illegal error

So i am getting the error ** Error: C:/Modeltech_pe_edu_10.3c/examples/HW6/alu.v(53): Register is illegal in left-hand side of continuous assignment for the assign statement [assign result = 32'd0;] any ideas why? i have tried moving that cluster…
user1914650
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Altera Quartus and modelsim

I am writing something in verilog in quartus, and appeared to me something strange, but pretty simple actually This code increments the address correctly module counter( input wire clock, input wire reset, output reg…
Douglas Cerqueira
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Issues Regarding Quartus Synthesis Running Time

I am running Quartus II 13.0sp1 (64-bit) Web Edition. I used to design my modules in ModelSim simulator. Unfortunately, when I tried to test my program using the Altera Kit via Quartus II 13.0sp1. It takes so long time to run the program. Beside the…
user3300910
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