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Questions tagged [modelsim]

ModelSim is a popular simulator and debugging environment for VHDL, Verilog and SystemC. It is used in electronic design automation for development and verification of electronic (mainly digital) modules and systems for implementation on field-programmable gate arrays or integrated circuits.

ModelSim is a product by Mentor Graphics to simulate systems written in one of the hardware description languages (HDLs) VHDL or Verilog or the system-level modeling language SystemC.

Depending on the license, ModelSim offers all or a subset of the following features:

  • Source code editor
  • Compiler
  • Simulator
  • Waveform viewer
  • Interactive debugging such as breakpoints, stepping etc.
  • Signal tracing (dataflow) analysis
  • Code coverage analysis
  • Functional coverage analysis
  • Project file management

ModelSim integrates these features in a single configurable GUI, however, it can also be scripted via the Tcl language and controlled through command-line parameters which allows for automation of simulation and verification tasks.

756 questions
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Correct Linux command to check the license availability and also the current license users?

I am looking for the Linux command to find the current users of the tool and also the number of license available. I also need to get the machine details in which the license are being used. I need to get the following details : 1) total number of…
Ram
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I got error when passing a parameterised class in system verilog instance

i tried to make an instance of this module it gave me the following error (unexpected '#', expecting class.). why ? what is the solution? here is the module,instance and the error in this link
Yehia Farouk
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unable to enter if else statement

I wrote a code like this: if (a) begin //some coding end else begin stage = 0; if (b) begin if (stage == 0) begin stage = 1; end else if (stage == 1)…
Avelyn Goh
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Compilation of vhdl code

I am constantly getting this message- "# Compile of 1stfile.vhd failed with 0 errors." whenever I am trying to compile my file "1stfile.vhd", what should I do ?
Nikhil Sen
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Im trying to make a right/left shifter using verilog but my output is xxxxx

module MyProject(A,B,k,right,F); input [31:0]A; input [31:0]B; input [4:0]k; input right; output reg [31:0]F; reg [31:0]F1; integer i,j; initial begin assign F1=(A&~B)+(~A&B); for(j=0;j
Reem
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