-2

Assume we have a D-flip-flop. in RTL simulation (No t_hold and t_setup here), If its data input and clk changes at the same time, what the output should be ? The value before clk rise or the value after it ?

To make it even harder, If a data_in and clock are connected to same wire. what should be the flop's output be ? zero all time ? or one all time ?

I tried the last case in ModelSim, and I get that the output is 1 all the time, while I expect it to be 0. I expect that the flop in RTL-simulation should simulate the value before the clock edge.

Ayman Mouallem
  • 7

1 Answers1

0

When you use a simulation you will see results depend on how this case interpreted in the simulator what you use.

As you wrote in simulation t_setup = 0, it means that you don't need to keep signal in that level (what should be caught by flip flop) some time before rising (or falling) edge of clock signal, but can be applied exactly in the same time with the rising (or falling) edge of clock.

Because you see all time of the simulation '1' on the output of flip flop

Roman
  • 375
  • 2
  • 7
  • Usually it will be the value before in verilog simulations, but it depends on the scheduler. I was prototyping on an emulator and found out that simulator always had the value after. In that case the verilog simulation was masking a bug in a behavioral memory model from the vendor. The input data was not supposed to be changing on that clock edge. – JDQ Nov 03 '17 at 04:09