Testbench in VHDL

Question

I have designed an entity multiply and an architecture which implements this entity, but I don't know how to write a testbench for that. In other words: how can I pass values to my architecture? I'm not sure if this codes is right at all, but I can't test it without passing values to it.

library ieee; 
use ieee.numeric_std.all; 
use ieee.std_logic_1164.all;

entity multiply is
port (
    in_A : in std_ulogic_vector(7 downto 0);
    in_B : in std_ulogic_vector(7 downto 0);
    out_Q : out std_ulogic_vector(15 downto 0)
);
end multiply;

architecture multiply_arch of multiply is
signal p0 : std_ulogic_vector(7 downto 0);
signal p1 : std_ulogic_vector(7 downto 0);
signal p2 : std_ulogic_vector(7 downto 0);
signal p3 : std_ulogic_vector(7 downto 0);
signal p4 : std_ulogic_vector(7 downto 0);
signal p5 : std_ulogic_vector(7 downto 0);
signal p6 : std_ulogic_vector(7 downto 0);
signal p7 : std_ulogic_vector(7 downto 0);
begin
p0 <= (7 downto 0 => in_A(0)) and in_B;
p1 <= (7 downto 0 => in_A(1)) and in_B;
p2 <= (7 downto 0 => in_A(2)) and in_B;
p3 <= (7 downto 0 => in_A(3)) and in_B; 
p4 <= (7 downto 0 => in_A(4)) and in_B;
p5 <= (7 downto 0 => in_A(5)) and in_B;
p6 <= (7 downto 0 => in_A(6)) and in_B; 
p7 <= (7 downto 0 => in_A(7)) and in_B;

out_Q(15 downto 1) <= std_ulogic_vector((unsigned(p0) + unsigned(p1&"0") + unsigned(p2&"00") + unsigned(p3&"000") + unsigned(p4&"0000") + unsigned(p5&"00000") + unsigned(p6&"000000") + unsigned(p7&"0000000")));
end architecture multiply_arch;

-1 Clearly homework. Clearly has not read their first chapter on VHDL coding, or which ever chapter deals with entity instantiations. — Philippe, May 05 '14 at 13:50

score 0 · Answer 1 · answered May 05 '14 at 12:30

You need to create a component definition and then instantiate that component in another file. This file will be your test bench file.

The test bench file will need to have the component which looks like this:

component multiply is
port (
    in_A : in std_ulogic_vector(7 downto 0);
    in_B : in std_ulogic_vector(7 downto 0);
    out_Q : out std_ulogic_vector(15 downto 0)
);
end component multiply;

Then below the begin statement for your architecture you need the component instantiation which will look something like this:

multiply_inst : multiply
port map (
    in_A  => test_A,
    in_B  => test_B,
    out_Q => test_out
);

You will need to drive signals test_A and test_B from your testbench, and look at the result of signal test_out to see if your multiply module is performing as expected.

For a complete example of this see: how to create a testbench in VHDL

score 0 · Answer 2 · answered May 05 '14 at 13:03

The multiply entity has few input bits (only 16 std_logic) and there is no clock or state in the module, so an exhaustive test bench that tries all 0/1 combinations of the inputs can be created. This test bench can include a "reference" model, which in the case of multiply operation simply is a *.

A suggestion for such an test bench is included below:

library ieee;
use ieee.std_logic_1164.all;

entity multiply_tb is
end entity;


library ieee;
use ieee.numeric_std.all;

architecture sim of multiply_tb is

  signal dut_in_a  : std_ulogic_vector( 7 downto 0);
  signal dut_in_b  : std_ulogic_vector( 7 downto 0);
  signal dut_out_q : std_ulogic_vector(15 downto 0);

  signal dut_ok : boolean;

begin

  -- Device Under Test (DUT)
  multiply_e : entity work.multiply
    port map(
        in_A => dut_in_a,
        in_B => dut_in_b,
        out_Q => dut_out_q);

  -- Result generation
  dut_ok <= to_integer(unsigned(dut_in_a)) * to_integer(unsigned(dut_in_b)) =
            to_integer(unsigned(dut_out_q(15 downto 1)));

  -- Stimuli generation and result test
  process is
    variable in_a_v  : natural;
    variable in_b_v  : natural;
    variable out_q_v : natural;
  begin
    for in_a_v in 0 to 255 loop
      for in_b_v in 0 to 255 loop
        dut_in_a <= std_ulogic_vector(to_unsigned(in_a_v, dut_in_a'length));
        dut_in_b <= std_ulogic_vector(to_unsigned(in_b_v, dut_in_b'length));
        wait for 5 ns;
        assert dut_ok report "DUT failed" severity ERROR;
        wait for 5 ns;
      end loop;
    end loop;
    wait;  -- End of simulation
  end process;

end architecture;

Note that it looks like there is some bug in the multiply entity, since bit 0 of out_Q is not driven, and the upper bits does not create proper multiply result. When the issue is fixed, then the result generation (reference model) should be updated as appropriate.

Think the test bench shows a pretty useful concept for verifying that kind of module, so maybe others may also benefit from the scheme. — Morten Zilmer, May 05 '14 at 13:17

Testbench in VHDL

2 Answers2