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Questions tagged [vivado]

Vivado® Design Suite is a development environment published by Xilinx for designing with their FPGA devices.

The Xilinx Vivado® Design Suite delivers a SoC-strength, IP-centric and system-centric, next generation development environment that has been built from the ground up to address the productivity bottlenecks in system-level integration and implementation. The Vivado Design suite is a Generation Ahead in overall productivity, ease-of-use, and system level integration capabilities.

http://www.xilinx.com/products/design-tools/vivado.html

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How to design a custom ip (axi compatible) to read and write from DDR (in Xilinx Vivado)

I have a design with Microblaze and MIG, which is tested through xsct for read and write from a 2GB DDR3 RAM. I would like to design a custom IP which would take commands (for block read and write from memory) through xsct and write to the RAM as…
vineeshvs
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How do I write this verilog testbench?

I am using Vivado to try to write a testbench for some Verilog code I wrote for an FSM. Here is the timing diagram which I derived from the state diagram: . Below is what I have so far: module testbench(); reg X_tb, clk_tb, rstn_tb; …
joasctorb
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Ignore I/o count when syntheis and implementation on vivado

I have a design that contains a lot of io so they are more than the io of the fbga My design will be connected to a top level module But for now I want to syntheis that without connecting the design IOs to fbga bins
A_S
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error while trying to run make command

I'm trying to clone and make this project to use in Vivado: https://github.com/olajep/parallella-fpga/tree/2016.11 after I've cloned it then I use git submodule init and the gir submodule update command. after that I used make command and I get this…
hadi nik
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How do I "nest" modules in Verilog?

I am making a single cycle cpu that follows MIPS assembly instructions and am wondering how to clean up the schematic. So for example I have several different modules instantiated together as shown by the code below. Now when this comes up under…
proCrow
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Basys3 board 4-bit counter, I don't know why its not producing bit-stream? Error in implementation

I wanted to make a 4-bit counter on Basys3 board using Vivado. I wrote a code for it in verilog. I am not able to generate the bit stream. I have pasted stopwatch.v module and constraint file. The onboard clock speed of Basys3 is…
Nipun Pruthi
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Getting initialized value in the waveform

Below is the testbench library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity prime_tb is end prime_tb; architecture Behavioral of prime_tb is COMPONENT prime_tb PORT( clk : in std_logic; reset : in std_logic; …
12345
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Indeterminate register values in hdl simulation

I am trying to simulate an AXI4(Full) master using Vivado. It is supposed to write the following values on the slave side(which, in my case, is gonna be some registers in my zedboard PS) 0x0000fe01 to 0xe000a204 0x0000fe01 to 0xe000a208 0x00000001…
Parth K
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Unspecified and Unconstrained logic ports Vivado

I have a code for a basic computer developed in VHDL. when I add a component for an I/O device, It fails to generate a Bitstream (it completes the synthesis and implementation), giving the following errors: [DRC NSTD-1] Unspecified I/O Standard: 54…
gramsch
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Vivado 2015.1 VHDL Input/ Output Violation

I am getting through the tutorial of Nexys 4 DDR and I am implementing a simple MUX library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VComponents.all; -- Uncomment the following library declaration if using -- arithmetic…
ayo
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vivado constraints problems with vhdl

I'm new on the use of vivado. I've problems with post synthesis timing simulation of an FSM. the simulation doesn't work how aspected( behavioral simulation and post synthesis functional simulation work). probably, there are some problems with…
Valerio
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How to declare a variable length std_logic_vector signal

I have a std_logic_vector input declared in my program, say number : std_logic_vector(7 downto 0). I want to declare a std_logic_vector type signal whose length goes on increasing till the length of my input 'number'. To be specific, I want a…
Veena
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Making Vivado Synthesis "A process triggered every clock cycle will not have functionality every clock cycle"

This is code for ALU that does addition and multiplication only. An addition is handled in same clock cycle but the multiplication result has to be delayed by 3 clock cycles. module my_addmul( //control signals input i_clk, input i_rst, …
Qazi
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VHDL package not compiling

I am new to VHDL and I'm using VIvado 2017.1. I'm trying to use a package to define constants and other such enumerated types to include in multiple models. Right now however, I am unable to use the package in my model. I keep getting Error:…
user5565748
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12bit ADC as input for CORDIC

I am new in DSP and this is problem for me. I need convert 12bit output from ADC to 2QN number format. It is input for CORDIC IP in Vivado. Output from CORDIC are two signals in 1QN format. Sin and Cos. Quadrature signal (I and Q) I need from CORDIC…
thomas810
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