How to design a custom ip (axi compatible) to read and write from DDR (in Xilinx Vivado)

Question

I have a design with Microblaze and MIG, which is tested through xsct for read and write from a 2GB DDR3 RAM.

I would like to design a custom IP which would take commands (for block read and write from memory) through xsct and write to the RAM as per the command.

Example: A command would ask the custom ip to do a block read (say from 128 locations) from a particular address.

I have tried to read custom IPs for interacting with DRAMs in Xilinx forum. (But couldn't locate the solution for this specific task)

Doubts

1. Is Microblaze or any processor needed to achieve this objective?
2. How can I design my custom IP (as I don't understand how Microblaze communicates with MIG). Where can I read about it? Or is it even necessary for this purpose?

Thanks :)

Answer 1

You can design your own DDR interface if you know a lot about electronics, timing, setting constraints, delay lines, auto timing calibration and asynchronous design. If not: don't try!

Where I worked DRR interfaces where always given to the most senior designers with 15+ years design experience and luckily I never had to design one (Maybe because the management thought I was not up to such a complex job :-)

When I read what you want:

A command would ask the custom ip to do a block read (say from 128 locations) from a particular address.

You can use standard a DDR3 IP block with an AXI interface. The AXI bus is sort of command oriented and the latest version supports block reads or writes of anything between 1 and 256 locations. The bus is normally 32 or even 64 bits wide so you get a block of 1K or 2K bytes back per read command.

No, you don't need a processor. You can make an AXI DMA engine which issues reads or writes. You need to read up on AXI though. The specification is freely available, but beware that the protocol is fiendish. It looks easy, but it is not! The devil is in the details with address and data buses which work independent.

As to complexity:
I have looked up an AXI ping-pong read DMA FSM I designed. It is ~130 lines of code. (Including lots of comment as it should!)