I am new to VHDL and I'm using VIvado 2017.1.
I'm trying to use a package to define constants and other such enumerated types to include in multiple models. Right now however, I am unable to use the package in my model. I keep getting
Error: Cannot find <PACKAGE NAME> in library <xil_defaultlib>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file
However the package in question is in the xil_defaultlib folder and I'm pretty sure it's compiled as I see no errors [as seen here][1].
My code for each is
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use work.Specs_Package.all;
entity Freq_Divider is
Port ( En,clk, reset : in std_logic; clock_out: out std_logic);
end Freq_Divider;
architecture bhv of Freq_Divider is
signal count: std_logic_vector(7 downto 0);
signal tmp : std_logic := '0';
begin
if rising_edge(reset) then
count <= x'00';
end if
process(clk,EN)
begin
if EN = '1' then
rising_edge(clk) then
count <= count + 1;
end if;
end if;
end process;
end bhv;and
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
PACKAGE SPECS_PACKAGE IS
--Freq Divider
--667Mhz clock
--667/23=29MHz 22 - 0x16
--667/29=23MHz 28 - 0x1C
--667/46=14.5MHz 45 - 0x2D
CONSTANT FREQ_DIVIDER_LIMIT : STD_LOGIC_VECTOR(7 DOWNTO 0) := X'1C';
END PACKAGE SPECS_PACKAGE;://i.stack.imgur.com/4b1vz.png
