Questions tagged [vivado]

Vivado® Design Suite is a development environment published by Xilinx for designing with their FPGA devices.

The Xilinx Vivado® Design Suite delivers a SoC-strength, IP-centric and system-centric, next generation development environment that has been built from the ground up to address the productivity bottlenecks in system-level integration and implementation. The Vivado Design suite is a Generation Ahead in overall productivity, ease-of-use, and system level integration capabilities.

http://www.xilinx.com/products/design-tools/vivado.html

744 questions

-1

votes

1 answer

Store data into ram on a zynq device

I am at moment having some problems storing an image generated in the PS part of my Zynq into the DDR3 of my board, and then read that image into the PL side of the board such that the VGA driver created there can The PS creates a 640x480 image,…

vhdl vivado zynq

asked May 01 '16 at 06:52

Lamda

-1

votes

6 answers

Multiple objects in a loop C++ without "new" keyword

I have a scenario where I need to create different objects in each iteration of a 'for' loop. The catch here is the synthesizer I am working does not support the "new" keyword. The Synthesizer I am using translates C/C++ code to RTL code (Hardware).…

c++ vhdl verilog synthesis vivado

asked Jan 12 '16 at 17:07

Nikhil Pratap

-1

votes

3 answers

How to only show differences in source files

I am currently trying to setup a Xilinx Vivado project on git. Problem is there are tons of annoying files that Vivado uses that I dont want to see in a file dif. I want to be able to clone the project elsewhere and have it just work. So I don't…

git vivado

asked Jan 10 '16 at 23:01

Brian Crafton

-1

votes

1 answer

Simulation error on vivado: A fatal run-time error was detected. Simulation cannot continue

I have the following error when I try to run a simulation with vivado: A fatal run-time error was detected. Simulation cannot continue. Any idea about the type of the error? Below my testbench: library ieee; use ieee.std_logic_1164.all; use…

vhdl xilinx vivado

asked Jul 13 '15 at 10:44

user3914897

-1

votes

4 answers

ambiguous clock in event control

I wrote such verilog code in xilinx vivado: module a(input clk, input clk1, output reg [4:0] acc) initial begin acc = 5'd0; end always @ (posedge clk or posedge clk1) begin acc <= acc+1; end endmodule And the error (ambiguous clock in event…

verilog xilinx vivado

asked Nov 26 '14 at 09:32

K2082

-2

votes

1 answer

How to use the command "+incdir+" in synplify script(.tcl) when one verilog file include another verilog file?

I insert a verilog file into another verilog file by using "`include " And when I used the synplify script(*.tcl) to try to synthesize, one error occured: invalid command name "+incdir+<...>" It seems like I have to use the command "+incdir+"…

verilog fpga vivado synthesis synplify

asked Aug 08 '23 at 09:41

Xiuhua Yang

-2

votes

1 answer

Why in the Design Timing Summery (synthesis) in Vivado i get WNS = inf?

I want to make sure that my program works with a clock of at least 100ns. I have already set the timing constraint.

vhdl vivado

asked Apr 09 '22 at 15:09

Gabriele Marchetti

-2

votes

1 answer

How can i use enum in a testbench while passing a file with vectors?

basically i declared a typedef enum in a package (in a file called Definition.sv): typedef enum logic[3:0] { AND = 4'b0000, //AND EOR = 4'b0001, //XOR …

enums verilog system-verilog hdl vivado

asked May 16 '21 at 20:21

Gabbed

-2

votes

1 answer

How to get all used IDs in a log file

I have a log file containing multiple IDs like this: INFO: [Synth 8-3491] module 'IOBUF' declared at 'C:/Xilinx/Vivado/2017.3/scripts/rt/data/unisim_comp.v:22655' bound to instance 'LED_tri_iobuf_7' of component 'IOBUF'…

regex bash grep vivado logfile-analysis

asked Mar 04 '18 at 00:23

Paebbels

15,573
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70
139

-2

votes

1 answer

ERROR: unable to find numeric literal operator 'operator""U'?

I am using ARM v7 g++ compiler on Vivado and SDK 2017.4. I had the same code working without any problem, but now it is throwing this error after changing something which is not related with this, apparently. I have undone the changes but it still…

c++ xilinx vivado zynq

asked Jan 29 '18 at 20:20

Cerilet

-2

votes

1 answer

Array aggregation on self-defined types?

I'm trying to implement an FSM with a RAM behavior. There are multiple addresses of this ram that should be initialized while describing this FSM. So, I'm using the array aggregation technique to initialize the first 20 addresses of the ram_block.…

vhdl hdl vivado

asked Jan 01 '18 at 10:32

hexpheus

-2

votes

1 answer

Coding error for vivado project

I wanted to synthesis this coding, but it keep telling me that there is error at "reg button_old, button_raise;". Is there anyone who knows what mistakes I have in the coding? Thank you very much for your help. We are doing project using nexys 4,…

verilog vivado

asked Dec 04 '17 at 07:15

Zur'ain Zulpata

-2

votes

1 answer

Synthesis Error IN VIVADO HLS

I wrote C++ Program to sum two numbers. During the Simulation I got correct result but in synthesis.Solution1/.autopilot/db/Adder.pragma.1.cpp:1, error. Please let me know, why I am getting that error message during Synthesis.

c++ c xilinx vivado vivado-hls

asked Mar 16 '17 at 08:58

Saras

-2

votes

1 answer

Vhdl Test Bench Unknown Syntax Error

I am trying to write a testbench but Vivado tells me that I have a Syntax error on a specific line. I am not able to realize what have I done wrong. Can anyone help. Here is my tb code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use…

testing syntax vhdl vivado

asked May 28 '15 at 10:04

George Timbakianakis

-3

votes

1 answer

How can I create a grayscale image for Vivado HLS?

How can I create a grayscale image in c++? Image size 100x100. I know that in python this can be done using numpy. The best option would be if this image looks like a scale of 10 colors from white to black. I work in Vivado HLS, so I can only use…

c++ fpga hdl vivado vivado-hls

asked Nov 25 '22 at 17:11

Тёма Ершов

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