Questions tagged [vivado]

Vivado® Design Suite is a development environment published by Xilinx for designing with their FPGA devices.

The Xilinx Vivado® Design Suite delivers a SoC-strength, IP-centric and system-centric, next generation development environment that has been built from the ground up to address the productivity bottlenecks in system-level integration and implementation. The Vivado Design suite is a Generation Ahead in overall productivity, ease-of-use, and system level integration capabilities.

http://www.xilinx.com/products/design-tools/vivado.html

744 questions

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Problem with adding different numbers to a register in Verilog (Vivado)

I'm currently in a university class learning about digital system design in Verilog using Vivado. My final project is an American football scoreboard. I'm working on implementing the score feature (for both teams), and I'm having an issue with…

asked Nov 12 '21 at 03:20

Matt Plexico

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1 answer

Sending serial data to FPGA design on ZedBoard

I've created a receiver design for a UART. Testing with stimuli on the testbench does indeed show correct functionality. What I am now to try is to test it on real hardware, but I am not sure how to be able to send data serially from the PC to the…

python serial-port fpga uart vivado

asked Oct 05 '21 at 19:02

abahadoran

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1 answer

In the below vhdl code though i have specified the range of variable it is counting endlessly. How to over come this problem

the temp variable is storing data out of its range. The range is used to store the maximum final value but it is holding the previous value and goes on incrementing. The functionality of for loop which is condition based is not satisfingenter image…

vhdl vivado

asked Oct 04 '21 at 11:32

sarath jaladi

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Shift n bits out of a register per clock

I am working in Vivado using Verilog. Assume I have 2 registers: reg [3327:0]a; reg [1023:0] b; Each clock cycle Id like to take the 13 bits from a and 4 bits from b and multiply them. Clock 1: a[12:0] * b[3:0] Clock 3: a[25:13] * b[7:4] What is…

verilog hdl vivado

asked Jul 05 '21 at 19:03

Daftyler

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2 answers

System Verilog FSM `next state` does not transition when `present state` value in next state combinatorial logic block transitions - ternary operator

in my Verilog code, the ns value does not get assigned to any of the values in the next state logic. As I coded the next state logic to assign a value to the ns state variable whenever there is a transition in the ps. Here is the FSM code snippet …

verilog system-verilog xilinx hdl vivado

asked Apr 11 '21 at 07:06

TheSprintingEngineer

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Xilinx - Vivado Project: VGA IO not working

I'm new to Xilinx-Vivado. So at the moment we just need to look and see how Vivado and SDK work using Zybo Zynq-7000 Board. I searched on the internet, and found a project with VGA IO. The mysterious thing is that I actually made it to work when I…

sdk vhdl fpga xilinx vivado

asked Jan 06 '21 at 17:02

Bobo RS

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1 answer

In Vivado, how to "Create Port" in a "Block Design" that is mapped to a "Board Definition File" port for PicoZed

Let's say I have some simple Verilog code for controlling an LED by turning it on and off every 1 second. I call it "blinker.v": module blinker( input wire sys_clk, input wire sys_rst_n, output wire [3:0] led ); …

verilog fpga xilinx vivado

asked Nov 05 '20 at 15:45

Bimo

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problem with the synthasizable version of vivado hls

i am implementing a simple image transformation filter in vivado hls. I have attached the files below: //headerfile- ct_h.hpp #include #include #include #include #include #define…

c++ opencv vivado vivado-hls

asked Jul 21 '20 at 13:31

mutyala mahesh

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1 answer

Vivado: setting timing constraints for input and output delay, simulation mismatch and wrong clock behavior

I'm implementing a hashing algorithm in Verilog using Vivado 2019.2.1. Everything (including synthesis and implementation) worked quite well but I noticed recently that the results of the behavioral simulation (correct hash digest) differs from the…

constraints verilog timing vivado

asked Jun 13 '20 at 14:17

Johannes

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System Verilog, how to sum array values?

I'm trying to sum array values using System Verilog. My data are declared like this: reg signed [23:0] n2 [31:0]; reg signed [15:0] w2 [195:0]; w2 is a reg with values stock in it. for(int i2=0; i2<32; i2++) begin for(int …

for-loop sum verilog system-verilog vivado

asked Mar 28 '20 at 10:42

user11557577

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1 answer

Vivado just points out that there is an exception

I'm trying to write a module which performs convolution on 24 by 24 bitmap image. And here is the DUT and testbench. Maybe there are some problems and I spend couple of hours to find what is problem but I can't figure it out. Additionally, RTL…

verilog hardware fpga vivado

asked Mar 03 '20 at 07:04

laurent01

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1 answer

Debounce Code Correction for a Decimal Counter Project in 1Hz counting Speed

I am completly new for the FPGA and basys3 development board. I have a project for Counter on the 7 segment displays on the board. We got 3 different layers as a design. cntr / cntr_rtl / cntr_top / cntr_top_struc / io_ctrl / io_ctrl_rtl / And…

button vhdl fpga vivado debouncing

asked Jan 18 '20 at 14:40

Excellency

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1 answer

Operating CORDIC IP VHDL

I have been looking extensively into the operation of the CORDIC IP for use with Sin and Cos in VHDL. According to page 24 of the CORDIC V6 documentation:…

vhdl vivado

asked Oct 09 '19 at 14:37

m1st3rnutso

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1 answer

R&W with AXI4 slave

I'm a begginer in VHDL and Vivado and I need to establish communication between slave and master; exactly I need to read and write. I mean, my slave is a memory and my master is a DDR controller. I used the wizard to create an IP but I am pretty…

vhdl xilinx firmware vivado vivado-hls

asked Jul 18 '19 at 14:35

Juanma Canals

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Verilog. Setting output as input in a ripple adder

I've started Verilog not too long ago and am stuck with some conditional statements in my ripple adder. I have a 6 bit ripple adder (that works) but I want to add an extra functionality. I have a 2 bit variable, called 'changer' that; if changer ==…

verilog fpga vivado synthesis

asked Feb 24 '19 at 18:55

E. Cheng

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