-1

I have a std_logic_vector input declared in my program, say number : std_logic_vector(7 downto 0). I want to declare a std_logic_vector type signal whose length goes on increasing till the length of my input 'number'. To be specific, I want a signal to do this -

for j in num_length downto 0 loop  --num_length=number'length-1
a <= number(num_length downto j); -- variable length signal 'a'
end loop;

How can I do this??

Veena
  • 37
  • 2
  • 9
  • use `number'length`. But your code example makes no sense. – JHBonarius Jun 16 '17 at 08:09
  • Ok. I will explain my question. For ex: I have number= "10101010" (A std_logic_vector of size 8) I want to declare a signal 'a' which should take a="1" a="10" a="101" a="1010" and so on as it goes down in the for loop. I am looking at a simple way to do this. Thanks! – Veena Jun 16 '17 at 08:42
  • so you want a `std_logic_vector` with variable length? How do you assume that works? you would need dynamic memory allocation. VHDL is a hardware description language. `std_logic_vector` represents a number of wires. How would you add or remove wires dynamically in a system? You fix the length of any array during instantiation. – JHBonarius Jun 16 '17 at 08:57
  • In short: No that's not possible. I would advice you to read a book or online articles about the main principles of VHDL and strong typing. VHDL is a hardware simulation and description language. You can't create or remove wires in a chip at runtime. (That's what you asked for...) – Paebbels Jun 16 '17 at 18:19

1 Answers1

-1

VHDL is a hardware description language(HDL). Your std_logic_vector is represented by wires and registers (physical components). Therefore, the size cannot change dynamically, but has to be determined pre-synthesis.

So use a std_logic_vector with the 'MAX' length you'll need, then only read the bits you need: 

constant zeros : std_logic_vector(MAX-1 downto 0) := (others => '0');
signal a,b     : std_logic_vector(MAX-1 downto 0);
...
a <= something;
...
b <= zeros(MAX-1 downto i) & a(i-1 downto 0); -- i is your dynamic index

This does not cover the case where you need to read the full vector though.

You could use a mask.. a bit messy :

use ieee.numeric_std.all; 
...
constant mask  : std_logic_vector(MAX-1 downto 0) := (others => '1');
signal a,b     : std_logic_vector(MAX-1 downto 0);
...
a <= something;
...
b <= std_logic_vector(shift_right(unsigned(mask), MAX-i)) and a; -- i is your dynamic index

Not sure what you want to do exactly, but these ideas should help.

Ril Dank
  • 105
  • 1
  • 11
  • Yeah. currently i'm trying with max length and trying to resize my signal. In your solution, how do you define mask? again it needs to be of variable length right? otherwise we will get errors. – Veena Jun 20 '17 at 11:45
  • Actually, I meant zero padding, even though you could do it with a mask as well... answer edited. – Ril Dank Jun 20 '17 at 18:10