Getting initialized value in the waveform

Question

Below is the testbench

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity prime_tb is
end prime_tb;

architecture Behavioral of prime_tb is

   COMPONENT prime_tb
    PORT(
        clk     : in std_logic;  
        reset   : in std_logic;   
        seq_in  : in std_logic_vector(15 downto 0);     
        seq_out : out std_logic
  );
  END COMPONENT;

  signal reset   : std_logic := '0';
  signal clk     : std_logic := '0';
  signal seq_in  : std_logic_vector(15 downto 0);
  signal seq_out : std_logic;
  constant clk_period : time := 10 ns;

  begin

     uut: prime_tb PORT MAP (
        clk     => clk,
        reset   => reset,
        seq_in  => seq_in,
        seq_out => seq_out
     );

     clk_process :process
       begin
            clk <= '0';
            wait for clk_period/2;
            clk <= '1';
            wait for clk_period/2;
       end process;

     stim_proc: process
       begin   
           seq_in <=  "0000000011111111";             
               wait for clk_period;  
           seq_in <=  "0000000000001111";             
               wait for clk_period;                 
         wait;         
      end process;

end Behavioral;

I am new to VHDL and I am writing a function that takes a 16-bit input binary value and determining if it is a prime number. The output is '0' or '1'('1' for true and '0' for false). But when I run the simulation, the waveform I got has uninitialized values. It appears that both of my seq_in and seq_out are uninitialized. See link below.

Error:

Can someone help me to fix it?

An image of the incomplete package DividerPackage does not provide a [mcve]. — , Mar 08 '18 at 23:33

score 2 · Answer 1 · answered Mar 08 '18 at 09:51

2

You have a typo in your UUT instantiation. You didn't mean this:

   COMPONENT prime_tb
    PORT(
        clk     : in std_logic;  
        reset   : in std_logic;   
        seq_in  : in std_logic_vector(15 downto 0);     
        seq_out : out std_logic
  );
  END COMPONENT;

and this:

 uut: prime_tb PORT MAP (
    clk     => clk,
    reset   => reset,
    seq_in  => seq_in,
    seq_out => seq_out
 );

You meant this:

   COMPONENT prime
    PORT(
        clk     : in std_logic;  
        reset   : in std_logic;   
        seq_in  : in std_logic_vector(15 downto 0);     
        seq_out : out std_logic
  );
  END COMPONENT;

and this:

 uut: prime PORT MAP (
    clk     => clk,
    reset   => reset,
    seq_in  => seq_in,
    seq_out => seq_out
 );

BTW: you're not driving the reset input to your UUT.

answered Mar 08 '18 at 09:51

Matthew Taylor

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And while not providing a [mcve], the picture of the function module doesn't use the variable i declaration (a loop statement with a for loop parameter specification as an iteration scheme dynamically elaborates it's i, IEEE Std 1076-2008 10.10 Loop statement, 14.6 Dynamic elaboration). Package DividerPackage (or function module in it's body) also requires a use clause making package numeric_std_unsigned available (for `p1 := p1 - b1;` and `p1 := p1 + b1;` used in restoring division) noting the use of package numeric_std. The `and reset = '0' expression in the elsif condition is not needed. – Mar 08 '18 at 16:43
Set the testbench as top module for simulation, not the DUT. I usually use "tb_" as prefix in all testbench signal names. This makes the hierachy clear. – user2099996 Mar 08 '18 at 19:08

Getting initialized value in the waveform

1 Answers1