Questions tagged [vivado]

Vivado® Design Suite is a development environment published by Xilinx for designing with their FPGA devices.

The Xilinx Vivado® Design Suite delivers a SoC-strength, IP-centric and system-centric, next generation development environment that has been built from the ground up to address the productivity bottlenecks in system-level integration and implementation. The Vivado Design suite is a Generation Ahead in overall productivity, ease-of-use, and system level integration capabilities.

http://www.xilinx.com/products/design-tools/vivado.html

744 questions

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2 answers

Is everything really a string in TCL?

And what is it, if it isn't? Everything I've read about TCL states that everything is just a string in it. There can be some other types and structures inside of an interpreter (for performance), but at TCL language level everything must behave just…

tcl xilinx vivado

asked Nov 28 '18 at 05:04

Anatol

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2 answers

change in endianness while ethernet transmission

I work with zedboard and vivado v2017.3. I am trying to send data stored in a register(slv_reg0 in PL section of Zynq) pointed by baseaddr_p in the following program. I use lwip echo server application to read this address and send it to the PC via…

c vivado zynq

asked May 18 '18 at 10:01

upasana

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1 answer

Simulating VHDL 2008 unconstrained array type in Vivado 2017.1

I have the following type type VECTOR_ARRAY_TYPE is array(natural range <>) of std_logic_vector; which I use in my entity as follows: entity mux is generic ( sel_width : positive := 2; data_width : positive := 3 ); port ( d :…

vhdl fpga vivado

asked Dec 27 '17 at 12:28

epsilon_j

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1 answer

combine ports to bram interface

I want to write an IP to store/read data using BRAM. What I have so far is using the (C)DMA to read memory mapped data out of the RAM and get an AXIS. Then I created a new source file in VHDL to accept the AXIS on one side which worked like a…

vhdl xilinx vivado

asked Oct 13 '17 at 14:23

akira hinoshiro

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0 answers

Is it possible to open a Vivado project via Tcl and export it via write_project_tcl as Tcl?

Xilinx Vivado can export the content of a *.xpr file (Xilinx Vivado project file) as Tcl. Therefore a Tcl command exists in GUI mode (project mode): write_project_tcl {C:/.../project/KC705.tcl} From a version control perspective, it's better to…

git tcl xilinx vivado

asked Oct 12 '17 at 05:25

Paebbels

15,573
13
70
139

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0 answers

7 Series Transceiver synthesis issue

I'm having some synthesis issues using 7 series GTX transceiver wizard in my project. I designed a basic custom protocol and a top level wrapper. In behavioral everything works just fine, but when synthesizing project the data bus attached to…

vhdl fpga vivado

asked Sep 29 '17 at 06:11

j.oak

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0 answers

What is the difference between using a 'constant' and using a number in vhdl

As part of adaptations to an existing large design on Artix-7 FPGA, I implemented a simple counting mechanism, something similar to "Archticture with 'constant' ", so that in the future, I can just change the value of the constant and not worry too…

vhdl fpga synthesis vivado

asked Sep 06 '17 at 11:30

Vinay Madapura

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4 answers

Function clogb2() generated by vivado can't synthesize with loop limit error

I'm trying to design an AXI_master peripheral with vivado. I used the axi peripheral generator in vivado menu and modified the vhdl code generated. In vhdl code there is a function clogb2 declared with following code: function clogb2 (bit_depth :…

vhdl vivado

asked Jun 23 '17 at 08:47

FabienM

3,421
23
45

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2 answers

initializing and using SD card after migration from vivado 2015.2 to 2016.4 does not work

--------------- EDIT: Additional Note ----------------------------------------- We just tried only migrating to Vivado 2016.1. With that version the SD card is working with the new functions, even if it destroys the audio codec somehow. Which is…

c sd-card xilinx vivado

asked Mar 13 '17 at 10:06

Delet0r

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3 answers

bare metal assembly program on Zynq without Vivado/SDK

I have a question for those familiar with the Xilinx Zynq and associated design tools.... Is it possible to compile and run C code for the Zynq 7010 (Zybo dev board), WITHOUT using the Xilinx toolchain (Vivado/SDK)? Is it possible to assemble and…

assembly arm xilinx vivado zynq

asked Jan 19 '17 at 20:55

asmvolatile

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1 answer

Is function return an array possible in Vivado HLS?

A function like that： int * getRandom( ) { static int r[10]; int i; /* set the seed */ srand( (unsigned)time( NULL ) ); for ( i = 0; i < 10; ++i) { r[i] = rand(); printf( "r[%d] = %d\n", i, r[i]); } return…

c arrays vivado vivado-hls

asked Aug 09 '16 at 02:27

Varrian

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2 answers

How to see content of look up table

Imagine we have a simple code for fpga, I want to know if there is any way to watch content of specific lookUp table after synthesis, actually that data that will be written in SRAM module test8(a,b,c ); input a ; input b ; output…

fpga xilinx vivado

asked Jul 06 '16 at 11:05

tohidprogram

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1 answer

Should be 1.001 us equal to 1001 ns in VHDL?

I'm currently writing a test to check whether the type time is synthesized / simulated properly in various FPGA vendor tools. One corner case is the usage of real literals as the abstract literal for time values, e.g.: 1.001 us. The IEEE Std.…

vhdl xilinx-ise quartus vivado

asked Jan 11 '16 at 17:32

Martin Zabel

3,589
3
19
34

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1 answer

I cannot get the Xilinx uartlite IP to work

Im attempting to use the Xilinx uartlite 2.0 IP with an AXI4-lite interface to transmit a byte without a microblaze processor. Unfortunately, all the ready signals remain low after I set the data and valid signals and the tx signal never transmits.…

vhdl verilog fpga xilinx vivado

asked Jun 06 '15 at 17:14

jwanga

4,166
4
26
27

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1 answer

Vivado HLS 2014.4.1 crash without any error on Ubuntu 14.10 x64

I am using clear installations of Ubuntu 14.10 x64 and Vivado Design Suite 2014.4 with update 1. Vivado runs, but Vivado HLS crashes on start without any error. user@user-Precision-M4800:/opt/Xilinx/Vivado_HLS/2014.4/bin$…

ubuntu fpga vivado

asked Apr 16 '15 at 18:24

Nic30g

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