Basys3 board 4-bit counter, I don't know why its not producing bit-stream? Error in implementation

Question

I wanted to make a 4-bit counter on Basys3 board using Vivado. I wrote a code for it in verilog. I am not able to generate the bit stream. I have pasted stopwatch.v module and constraint file. The onboard clock speed of Basys3 is 100MHz.

//`timescale 1ns/1ps

module stopwatch( input clk, input reset, input start, input pause, output reg [3:0] out);

   reg [26:0] clock;
   reg        starter;


   always @(posedge clk or posedge reset)
     begin
    if (reset)
      begin
         out <= 0;
         clock <= 0;
      end

    else if (starter)
      begin
         if (clock == 25'd10000000)
           begin
          out <= out + 1'b1;
          clock <= 0;
           end
         else
             clock <= clock + 1'b1;
      end
     end // always @ (posedge clk or posedge reset)

   always @(*)
     begin
    if (start)
      starter <= 1'b1;
    else if (pause)
      starter <= 0;

     end

endmodule // stopwatch

Constraint_file.xdc

set_property PACKAGE_PIN U18 [get_ports {reset}]
set_property PACKAGE_PIN T18 [get_ports {start}]
set_property PACKAGE_PIN U17 [get_ports {pause}]
set_property PACKAGE_PIN U16 [get_ports {out[0]}]
set_property PACKAGE_PIN E19 [get_ports {out[1]}]
set_property PACKAGE_PIN U19 [get_ports {out[2]}]
set_property PACKAGE_PIN V19 [get_ports {out[3]}]



    set_property PACKAGE_PIN W5 [get_ports clk] 
    create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports {reset start pause out}]

Below is the error I am keep getting:

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
    < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pause_IBUF] >

    pause_IBUF_inst (IBUF.O) is locked to IOB_X0Y14
     and pause_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0

score 0 · Answer 1 · answered Mar 12 '18 at 17:59

The tools is complaining about your choice for the 'pause' I/O buffer.
It says you should use a global clock buffer input (BUFG) for that signal. It has routed the signal through a global clock buffer "BUFGCTRL_X0Y0".

This might have to do with the fact that 'starter' is a latch and Vivado thinks your pause signal is a clock. This piece of code is wrong:

always @(*)
begin
if (start)
  starter <= 1'b1;
else if (pause)
  starter <= 0;
end

First of all: In an always combinatorial block you do not use non-blocking assignments. You use '='
Secondly : there is no closing 'else' so you get a latch.

Or was this the code you wanted:

assign starter = start & ~pause;

Alternative you could move that code, as it is, into your clocked section. In that case make sure you reset "starter" as well.

Actually, I am mapping the push buttons for 'start' and 'pause'. If I use "assign starter = start & ~pause", the intended function may not be achieved. Its that if I pause it, then it will stay pause even after the releasing the "pause push botton". — Nipun Pruthi, Mar 18 '18 at 11:53
You then first have to make a paused 'toggle' signal. Also may have to de-bounce the incoming button signals. — Oldfart, Mar 18 '18 at 12:21

Basys3 board 4-bit counter, I don't know why its not producing bit-stream? Error in implementation

1 Answers1