How do I write this verilog testbench?

Question

I am using Vivado to try to write a testbench for some Verilog code I wrote for an FSM. Here is the timing diagram which I derived from the state diagram:

timing diagram .

Original FSM

Below is what I have so far:

module testbench();
     reg X_tb, clk_tb, rstn_tb;
     wire S_tb, V_tb;

     statemachine statemachine_tb(X_tb, clk_tb, rstn_tb, S_tb, V_tb);

     initial begin
          #10 X_tb = 0;
     end
endmodule

If X_tb and clk_tb are inputs and S_tb and V_tb are outputs, how do I include timing for S_tb and V_tb? I keep getting an error saying I can't use wire variables.

you need to provide error messages as well as definitions of your `statmachine` module. — Serge, Sep 27 '18 at 01:29

score 1 · Answer 1 · edited Oct 03 '18 at 06:33

S_tb and V_tb are the expected outputs which are asserted by the design module which in this case is "statemachine". The test bench encompasses the design, it acts as a stimulus for your design. In this case you will apply inputs like

initial
begin
 rstn_tb = 0; //assuming an active low reset
 clk_tb  = 0;
 #10 X_tb = 0;
end
always  
#5 clk_tb = ~clk_tb; //generates a clock having a frequency of 100MHz

The above inputs are passed on-to the statemachine module and in response to that the statemachine module generates some result which is received at the ports S_tb & V_tb.

Also while instantiating the module its better to use the dot-name convention like

module half_add(a,b,sum,carry); //half adder, partially written
 input a,b;
 output sum,carry;
 //logic
 endmodule

module full_add(a,b,cin,sum,carry)
 input a,b,cin;
 output sum,carry;
 //wires are not declared
 //instantiating half_add
 half_add h1(.a(w1),
        .b(w2),
        .sum(sum1),
        .carry(carry1)
    );

half_add h2(
 //similar call as h1 instance
   );
endmodule

The above type of instance avoids errors now if I instantiate the module like the one below

half_add h1(w1,
        w2,
        sum1,
        carry1
);

Here the ports are connected based on the position and one may make mistakes while writing this like accidentally one may write

half_add h1(w1,
        w2,
        carry1,
        sum1
);

This will cause carry1 to be connected to the sum port of the half adder module resulting in erroneous output. Hence I suggest you to avoid such type of instance calling. I guess that could be the reason for the error.

score 0 · Answer 2 · answered Oct 02 '18 at 04:01

You don't need to provide timing delays for your state machine outputs. You are building a synchronous design; therefore the outputs should simply be sampled on the relevant clock edges (falling edge from your instructions). You can do this by embedding the following line in your testbench everytime you want to wait for a clock edge:

@ (negedge clk_tb)

You can then capture the outputs or directly perform comparisons to expected values. Then change your input stimulus and wait for another clock edge and repeat for your next comparison.

How do I write this verilog testbench?

2 Answers2