vivado constraints problems with vhdl

Question

I'm new on the use of vivado. I've problems with post synthesis timing simulation of an FSM. the simulation doesn't work how aspected( behavioral simulation and post synthesis functional simulation work). probably, there are some problems with constraints( I use constraints wizard to create them). clock frequency=200 hz.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity control_asy_gate is
  Port ( clk : in STD_LOGIC;
     rst_in : in STD_LOGIC;
     full : in STD_LOGIC;
     fine : in STD_LOGIC;
     empty : in STD_LOGIC;
     busy : in STD_LOGIC;
     rst_out : out STD_LOGIC;
     data_valid : out STD_LOGIC;
     en_rom : out STD_LOGIC;
     en_comp : out STD_LOGIC;
     en_divisore : out STD_LOGIC;
     en_trasm : out STD_LOGIC);
 end control_asy_gate;

architecture Behavioral of control_asy_gate is

TYPE stati IS (init,trasmetti,compara,acquisizione,reset);
SIGNAL state: stati;
SIGNAL counter_rst: integer range 0 to 2:=0;


begin
en_divisore<= not fine;
comb: PROCESS (clk,rst_in, full, empty,state,busy)
begin

 if rst_in='1' then
    state<=init; 
   counter_rst<=0;   
 else

 CASE state IS 
    WHEN init=>
          if rising_edge(clk) then
              state<= reset;
          end if;     
    WHEN reset=>
      if rising_edge(clk) then
         if counter_rst=2 then
             state<= trasmetti;
             counter_rst<=0;                      
         else
            counter_rst<=counter_rst+1;
            state<= reset;
         end if;
       end if;
    WHEN trasmetti=>
        if full='1' then
          state<= compara;
        else
          state<= trasmetti;               
        end if;

    WHEN compara=> 
       if empty='1' then                                  
          state<= acquisizione; 
      else             
          state<= compara;      
      end if;  
    WHEN acquisizione=>
         if busy='1' then
                state<=trasmetti;                 
         else
             state<=acquisizione;       
         end if;            
  end CASE;
end if; 
end process;

PROCESS (state)
begin

 CASE state IS 
   WHEN init=> 
     en_rom<='0';
     rst_out<='0';      
     en_trasm<='0';
     en_comp<='0'; 
     data_valid<='0';

   WHEN reset=>
      rst_out<='1';
      en_trasm<='0';
      en_comp<='0';
      en_rom<='0';
      data_valid<='0';

   WHEN trasmetti=> 
       en_rom<='1';
       rst_out<='0';      
       en_trasm<='1';
       en_comp<='0';
       data_valid<='0'; 

   WHEN compara=>
      en_rom<='1';
      rst_out<='0'; 
      en_trasm<='0';
      en_comp<='1';
      data_valid<='0';

    WHEN acquisizione=> 
          en_rom<='0';
          rst_out<='0';      
          en_trasm<='0';
          en_comp<='0';
          data_valid<='1';  
  end CASE;
end process;
end Behavioral;

CONSTRAINTS:

 create_clock -period 5000000000.000 -name clk -waveform {0.0002500000000.000} [get_ports clk]
create_generated_clock -name {state_reg[0]__0_LDC_n_0} -source [get_pins{state_reg[0]__0_LDC/G}] -divide_by 1 [get_pins {state_reg[0]__0_LDC/Q}]
 create_generated_clock -name {state_reg[0]__0_P_n_0} -source [get_ports clk] -divide_by 1 [get_pins {state_reg[0]__0_P/Q}]
 create_generated_clock -name {state_reg[1]__0_P_n_0} -source [get_ports clk] -divide_by 1 [get_pins {state_reg[1]__0_P/Q}]
 create_generated_clock -name {state_reg[2]__0_C_n_0} -source [get_ports clk] -divide_by 1 [get_pins {state_reg[2]__0_C/Q}]
 create_generated_clock -name {state_reg__0[0]} -source [get_ports clk] -divide_by 1 [get_pins {state_reg[0]/Q}]
 create_generated_clock -name {state_reg__0[2]} -source [get_ports clk] -divide_by 1 [get_pins {state_reg[2]/Q}]
 set_input_delay -clock [get_clocks clk] -min -add_delay 1.210 [get_ports busy]
 set_input_delay -clock [get_clocks clk] -max -add_delay 2.250 [get_ports busy]
set_input_delay -clock [get_clocks clk] -clock_fall -min -add_delay 1.210 [get_ports empty]
set_input_delay -clock [get_clocks clk] -clock_fall -max -add_delay 2.250 [get_ports empty]
set_input_delay -clock [get_clocks clk] -min -add_delay 1.210 [get_ports empty]
 set_input_delay -clock [get_clocks clk] -max -add_delay 2.250 [get_ports empty]
set_input_delay -clock [get_clocks clk] -clock_fall -min -add_delay 1.210 [get_ports full]
 set_input_delay -clock [get_clocks clk] -clock_fall -max -add_delay 2.250 [get_ports full]
set_input_delay -clock [get_clocks clk] -min -add_delay 1.210 [get_ports full]
set_input_delay -clock [get_clocks clk] -max -add_delay 2.250 [get_ports full]
set_input_delay -clock [get_clocks clk] -clock_fall -min -add_delay 1.210 [get_ports rst_in]
set_input_delay -clock [get_clocks clk] -clock_fall -max -add_delay 4.250 [get_ports rst_in]
set_input_delay -clock [get_clocks clk] -min -add_delay 1.210 [get_ports rst_in]
set_input_delay -clock [get_clocks clk] -max -add_delay 4.250 [get_ports rst_in]
create_clock -period 100.000 -name virtual_clock
set_input_delay -clock [get_clocks virtual_clock] -min -add_delay 1.000 [get_ports fine]
set_input_delay -clock [get_clocks virtual_clock] -max -add_delay 6.000 [get_ports fine]
set_output_delay -clock [get_clocks virtual_clock] -min -add_delay 8.000 [get_ports en_divisore]
set_output_delay -clock [get_clocks virtual_clock] -max -add_delay 15.000 [get_ports en_divisore]

Can you help me to understand where I wrong and how resolve this problem?

The process `comb` is mixing up sequential and combinational logic. At first, you should check the RTL rather than the constraints. — , Jul 29 '17 at 22:42
Please google regarding proper synchronous process syntax in VHDL. There are many examples online. You are for instance missing `rising_edge(clk)`. Also check the FPGA/ASIC tool manufacturer's documentation on VHDL synthesis guidelines — JHBonarius, Jul 30 '17 at 10:21

score 0 · Answer 1 · edited Sep 22 '17 at 14:07

0

ahmedus is right: your code is not Register Transfer Level (RTL). It will synthesize differently than what you expect. Your constraints wizard identified a lot of clocks that should be regular logic signals. This is the sign that your code is not correct with respect to what you want to design. Separate the synchronous process (only clock and reset in the sensitivity list) and combinatorial.

edited Sep 22 '17 at 14:07

Graham

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answered Jul 30 '17 at 08:40

Renaud Pacalet

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vivado constraints problems with vhdl

1 Answers1