Unspecified and Unconstrained logic ports Vivado

Question

I have a code for a basic computer developed in VHDL. when I add a component for an I/O device, It fails to generate a Bitstream (it completes the synthesis and implementation), giving the following errors:

[DRC NSTD-1] Unspecified I/O Standard: 54 out of 54 logical ports use I/O
standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific
value. This may cause I/O contention or incompatibility with the board
power or connectivity affecting performance, signal integrity or in
extreme cases cause damage to the device or the components to which it is
connected. To correct this violation, specify all I/O standards. This
design will fail to generate a bitstream unless all logical ports have a
user specified I/O standard value defined. To allow bitstream creation
with unspecified I/O standard values (not recommended), use this command:
set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using
the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this
command to a .tcl file and add that file as a pre-hook for write_bitstream
step for the implementation run. Problem ports: a[15:0], b[15:0],
sop[2:0], result[15:0], c, z, and n.


[DRC UCIO-1] Unconstrained Logical Port: 54 out of 54 logical ports have
no user assigned specific location constraint (LOC). This may cause I/O
contention or incompatibility with the board power or connectivity
affecting performance, signal integrity or in extreme cases cause damage
to the device or the components to which it is connected. To correct this
violation, specify all pin locations. This design will fail to generate a
bitstream unless all logical ports have a user specified site LOC
constraint defined.  To allow bitstream creation with unspecified pin
locations (not recommended), use this command: set_property SEVERITY
{Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs
infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl
file and add that file as a pre-hook for write_bitstream step for the
implementation run.  Problem ports: a[15:0], b[15:0],
sop[2:0],result[15:0], c, z, and n.

The signals I added are:

signal lcdout           : std_logic;
signal disout           : std_logic;
signal ledout           : std_logic

And the instance of the new components are:

inst_RegDis: Reg Port map (
     clock    => clock,
     load     => disout,
     datain   => alu_A,
     dataout  => dis
);

inst_RegLed: Reg Port map (
     clock    => clock,
     load     => ledout,
     datain   => alu_A,
     dataout  => led
);

inst_DecoderOut: Decoder_Out Port map(
     data_in => alu_B,
      lcdout => load,
      disout => disout,
      ledout => ledout
);

Finally, the component that have the problem ports is:

inst_ALU: ALU Port map (
       a  => alu_A,
       b  => alu_B,
       sop => selALU,
       c  =>  alu_c,
       z  =>  alu_z,
       n  =>  alu_n,
       result => alu_result
       );

As soon as I comment the new signals and components the problem goes away, ALU and decoder out share a signal, but It doesn't change anything in the ALU component. Any idea of what may be causing this problem?

Possible duplicate of [Vivado 2015.1 VHDL Input/ Output Violation](https://stackoverflow.com/questions/47348146/vivado-2015-1-vhdl-input-output-violation) — , Nov 25 '17 at 21:27
I looked it before, but the difference is that my ALU component only use logical ports from inside, and it doesn't give any errors without the Decoder or the other 2 Reg instances, so is like the ALU signals disconnect when I add the others — gramsch, Nov 26 '17 at 00:14
Post your constraints file. Without it, your question is incomplete, and we cannot help. — Oron Port, Nov 26 '17 at 02:22
You probably do not have a constraints file. At least, this would not be the first time I see someone try to synthesize VHDL for an FPGA, expecting the FPGA tool to miraculously read his mind to understand how he wants the logic to be connected to the pins. — JHBonarius, Nov 26 '17 at 12:51

score 0 · Answer 1 · answered Nov 26 '17 at 13:14

You need to specify the pin locations and I/O standards in a Xilinx Design Constraints (XDC) file.

Btw. you can not implement a bare ALU in an FPGA device and test it on a development board. You need further input and output handling. E.g. debounce circuits, a 7-Segment display driver, low-active signal inversion ...

More over your design requires 54 I/Os, do you have a development board with so many user I/O?

score 0 · Answer 2 · answered Nov 28 '17 at 01:24

0

The problem was that I added a signal when there already was one with that purpose. When you have a signal that is only connected to one end (in this case the lcdout wasn't connected to Decoder_out yet) it sends this error in the write bitstream, because it can cause a data corruption. Why this signal made a problem to an unrelated component (ALU) still puzzles me.

answered Nov 28 '17 at 01:24

gramsch

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You just provide an error, some snippets of code and a solutions that works for you. It was already very difficult to help you this way, but now that it is resolved, this question doesn't add any useful information for others. – JHBonarius Nov 28 '17 at 09:16

Unspecified and Unconstrained logic ports Vivado

2 Answers2